Microchip Technology Inc. ATSAMC21N17A 2024.06.03 Microchip ATSAMC21N17A Microcontroller CM0+ r0p0 selectable true 2 false 8 32 AC Analog Comparators AC 0x0 0x0 0x40 registers n 0x0 0x24 registers n AC_INTREQ 27 AC 27 COMPCTRL0 Comparator Control n 0x20 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 VSCALE VDD Scaler 0x4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x3 SWAP Swap Inputs and Invert 15 1 COMPCTRL1 Comparator Control n 0x34 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 VSCALE VDD Scaler 0x4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x3 SWAP Swap Inputs and Invert 15 1 COMPCTRL2 Comparator Control n 0x4C 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 VSCALE VDD Scaler 0x4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x3 SWAP Swap Inputs and Invert 15 1 COMPCTRL3 Comparator Control n 0x68 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 VSCALE VDD Scaler 0x4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x3 SWAP Swap Inputs and Invert 15 1 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 write-only CTRLB Control B 0x1 8 write-only n 0x0 0x0 START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 START2 Comparator 2 Start Comparison 2 1 START3 Comparator 3 Start Comparison 3 1 DBGCTRL Debug Control 0x9 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x2 16 read-write n 0x0 0x0 COMPEI0 Comparator 0 Event Input Enable 8 1 COMPEI1 Comparator 1 Event Input Enable 9 1 COMPEI2 Comparator 2 Event Input Enable 10 1 COMPEI3 Comparator 3 Event Input Enable 11 1 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 COMPEO2 Comparator 2 Event Output Enable 2 1 COMPEO3 Comparator 3 Event Output Enable 3 1 INVEI0 Comparator 0 Input Event Invert Enable 12 1 INVEI1 Comparator 1 Input Event Invert Enable 13 1 INVEI2 Comparator 2 Input Event Invert Enable 14 1 INVEI3 Comparator 3 Input Event Invert Enable 15 1 WINEO0 Window 0 Event Output Enable 4 1 WINEO1 Window 1 Event Output Enable 5 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 COMP2 Comparator 2 Interrupt Enable 2 1 COMP3 Comparator 3 Interrupt Enable 3 1 WIN0 Window 0 Interrupt Enable 4 1 WIN1 Window 1 Interrupt Enable 5 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 COMP2 Comparator 2 Interrupt Enable 2 1 COMP3 Comparator 3 Interrupt Enable 3 1 WIN0 Window 0 Interrupt Enable 4 1 WIN1 Window 1 Interrupt Enable 5 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 COMP2 Comparator 2 2 1 COMP3 Comparator 3 3 1 WIN0 Window 0 4 1 WIN1 Window 1 5 1 SCALER0 Scaler n 0x18 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER1 Scaler n 0x25 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER2 Scaler n 0x33 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER3 Scaler n 0x42 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 STATUSA Status A 0x7 8 read-only n 0x0 0x0 STATE0 Comparator 0 Current State 0 1 read-only STATE1 Comparator 1 Current State 1 1 read-only STATE2 Comparator 2 Current State 2 1 read-only STATE3 Comparator 3 Current State 3 1 read-only WSTATE0 Window 0 Current State 4 2 read-only WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 WSTATE1 Window 1 Current State 6 2 read-only WSTATE1Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 STATUSB Status B 0x8 8 read-only n 0x0 0x0 READY0 Comparator 0 Ready 0 1 read-only READY1 Comparator 1 Ready 1 1 read-only READY2 Comparator 2 Ready 2 1 read-only READY3 Comparator 3 Ready 3 1 read-only SYNCBUSY Synchronization Busy 0x20 32 read-only n 0x0 0x0 COMPCTRL0 COMPCTRL 0 Synchronization Busy 3 1 read-only COMPCTRL1 COMPCTRL 1 Synchronization Busy 4 1 read-only COMPCTRL2 COMPCTRL 2 Synchronization Busy 5 1 read-only COMPCTRL3 COMPCTRL 3 Synchronization Busy 6 1 read-only ENABLE Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only WINCTRL WINCTRL Synchronization Busy 2 1 read-only WINCTRL Window Control 0xA 8 read-write n 0x0 0x0 WEN0 Window 0 Mode Enable 0 1 WEN1 Window 1 Mode Enable 4 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0x0 INSIDE Interrupt on signal inside window 0x1 BELOW Interrupt on signal below window 0x2 OUTSIDE Interrupt on signal outside window 0x3 WINTSEL1 Window 1 Interrupt Selection 5 2 WINTSEL1Select ABOVE Interrupt on signal above window 0x0 INSIDE Interrupt on signal inside window 0x1 BELOW Interrupt on signal below window 0x2 OUTSIDE Interrupt on signal outside window 0x3 ADC0 Analog Digital Converter ADC 0x0 0x0 0x2C registers n 0x0 0x2E registers n ADC0_INTREQ 25 ADC0 25 ADC_AVGCTRL Average Control 0xC 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xa ADC_CALIB Calibration 0x2C 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 ADC_CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run During Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 ADC_CTRLB Control B 0x1 8 read-write n 0x0 0x0 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 ADC_CTRLC Control C 0xA 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 3 1 DIFFMODE Differential Mode 0 1 DUALSEL Dual Mode Trigger Selection 12 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0x0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 0x1 FREERUN Free Running Mode 2 1 LEFTADJ Left-Adjusted Result 1 1 R2R Rail-to-Rail mode enable 7 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0x0 MODE1 RESULT > WINLT 0x1 MODE2 RESULT < WINUT 0x2 MODE3 WINLT < RESULT < WINUT 0x3 MODE4 !(WINLT < RESULT < WINUT) 0x4 ADC_DBGCTRL Debug Control 0x1C 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 ADC_EVCTRL Event Control 0x3 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Satrt Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 ADC_GAINCORR Gain Correction 0x12 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 ADC_INPUTCTRL Input Control 0x8 16 read-write n 0x0 0x0 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1a SCALEDIOVCC 1/4 Scaled I/O Supply 0x1b DAC DAC Output 0x1c AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xa AIN11 ADC AIN11 Pin 0xb ADC_INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 ADC_INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 ADC_INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 ADC_OFFSETCORR Offset Correction 0x14 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 ADC_REFCTRL Reference Control 0x2 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 DAC DAC 0x4 INTVCC2 VDDANA 0x5 ADC_RESULT Result 0x24 16 read-only n 0x0 0x0 RESULT Result Value 0 16 read-only ADC_SAMPCTRL Sample Time Control 0xD 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 ADC_SEQCTRL Sequence Control 0x28 32 read-write n 0x0 0x0 SEQEN Enable Positive Input in the Sequence 0 32 ADC_SEQSTATUS Sequence Status 0x7 8 read-only n 0x0 0x0 SEQBUSY Sequence Busy 7 1 read-only SEQSTATE Sequence State 0 5 read-only ADC_SWTRIG Software Trigger 0x18 8 read-write n 0x0 0x0 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 ADC_SYNCBUSY Synchronization Busy 0x20 16 read-only n 0x0 0x0 AVGCTRL AVGCTRL Synchronization Busy 4 1 read-only CTRLC CTRLC Synchronization Busy 3 1 read-only ENABLE ENABLE Synchronization Busy 1 1 read-only GAINCORR GAINCORR Synchronization Busy 8 1 read-only INPUTCTRL INPUTCTRL Synchronization Busy 2 1 read-only OFFSETCORR OFFSETCTRL Synchronization Busy 9 1 read-only SAMPCTRL SAMPCTRL Synchronization Busy 5 1 read-only SWRST SWRST Synchronization Busy 0 1 read-only SWTRIG SWTRG Synchronization Busy 10 1 read-only WINLT WINLT Synchronization Busy 6 1 read-only WINUT WINUT Synchronization Busy 7 1 read-only ADC_WINLT Window Monitor Lower Threshold 0xE 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 ADC_WINUT Window Monitor Upper Threshold 0x10 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 AVGCTRL Average Control 0xC 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xA CALIB Calibration 0x2C 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run During Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0x0 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 CTRLC Control C 0xA 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 3 1 DIFFMODE Differential Mode 0 1 DUALSEL Dual Mode Trigger Selection 12 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 FREERUN Free Running Mode 2 1 LEFTADJ Left-Adjusted Result 1 1 R2R Rail-to-Rail mode enable 7 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit 0x0 16BIT 16-bit averaging mode 0x1 10BIT 10-bit 0x2 8BIT 8-bit 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 DBGCTRL Debug Control 0x1C 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x3 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Start Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x12 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 INPUTCTRL Input Control 0x8 16 read-write n 0x0 0x0 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 GND Internal Ground 0x18 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1A SCALEDIOVCC 1/4 Scaled I/O Supply 0x1B DAC DAC Output 0x1C AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xA AIN11 ADC AIN11 Pin 0xB INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 OFFSETCORR Offset Correction 0x14 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x2 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 DAC DAC 0x4 INTVCC2 VDDANA 0x5 RESULT Result 0x24 16 read-only n 0x0 0x0 RESULT Result Value 0 16 read-only SAMPCTRL Sample Time Control 0xD 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 SEQCTRL Sequence Control 0x28 32 read-write n 0x0 0x0 SEQEN Enable Positive Input in the Sequence 0 32 SEQSTATUS Sequence Status 0x7 8 read-only n 0x0 0x0 SEQBUSY Sequence Busy 7 1 read-only SEQSTATE Sequence State 0 5 read-only SWTRIG Software Trigger 0x18 8 read-write n 0x0 0x0 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 SYNCBUSY Synchronization Busy 0x20 16 read-only n 0x0 0x0 AVGCTRL AVGCTRL Synchronization Busy 4 1 read-only CTRLC CTRLC Synchronization Busy 3 1 read-only ENABLE ENABLE Synchronization Busy 1 1 read-only GAINCORR GAINCORR Synchronization Busy 8 1 read-only INPUTCTRL INPUTCTRL Synchronization Busy 2 1 read-only OFFSETCORR OFFSETCTRL Synchronization Busy 9 1 read-only SAMPCTRL SAMPCTRL Synchronization Busy 5 1 read-only SWRST SWRST Synchronization Busy 0 1 read-only SWTRIG SWTRG Synchronization Busy 10 1 read-only WINLT WINLT Synchronization Busy 6 1 read-only WINUT WINUT Synchronization Busy 7 1 read-only WINLT Window Monitor Lower Threshold 0xE 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x10 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 ADC1 Analog Digital Converter ADC 0x0 0x0 0x2C registers n 0x0 0x2E registers n ADC1_INTREQ 26 ADC_AVGCTRL Average Control 0xC 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xa ADC_CALIB Calibration 0x2C 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 ADC_CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run During Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 ADC_CTRLB Control B 0x1 8 read-write n 0x0 0x0 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 ADC_CTRLC Control C 0xA 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 3 1 DIFFMODE Differential Mode 0 1 DUALSEL Dual Mode Trigger Selection 12 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0x0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 0x1 FREERUN Free Running Mode 2 1 LEFTADJ Left-Adjusted Result 1 1 R2R Rail-to-Rail mode enable 7 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0x0 MODE1 RESULT > WINLT 0x1 MODE2 RESULT < WINUT 0x2 MODE3 WINLT < RESULT < WINUT 0x3 MODE4 !(WINLT < RESULT < WINUT) 0x4 ADC_DBGCTRL Debug Control 0x1C 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 ADC_EVCTRL Event Control 0x3 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Satrt Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 ADC_GAINCORR Gain Correction 0x12 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 ADC_INPUTCTRL Input Control 0x8 16 read-write n 0x0 0x0 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1a SCALEDIOVCC 1/4 Scaled I/O Supply 0x1b DAC DAC Output 0x1c AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xa AIN11 ADC AIN11 Pin 0xb ADC_INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 ADC_INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 ADC_INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 ADC_OFFSETCORR Offset Correction 0x14 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 ADC_REFCTRL Reference Control 0x2 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 DAC DAC 0x4 INTVCC2 VDDANA 0x5 ADC_RESULT Result 0x24 16 read-only n 0x0 0x0 RESULT Result Value 0 16 read-only ADC_SAMPCTRL Sample Time Control 0xD 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 ADC_SEQCTRL Sequence Control 0x28 32 read-write n 0x0 0x0 SEQEN Enable Positive Input in the Sequence 0 32 ADC_SEQSTATUS Sequence Status 0x7 8 read-only n 0x0 0x0 SEQBUSY Sequence Busy 7 1 read-only SEQSTATE Sequence State 0 5 read-only ADC_SWTRIG Software Trigger 0x18 8 read-write n 0x0 0x0 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 ADC_SYNCBUSY Synchronization Busy 0x20 16 read-only n 0x0 0x0 AVGCTRL AVGCTRL Synchronization Busy 4 1 read-only CTRLC CTRLC Synchronization Busy 3 1 read-only ENABLE ENABLE Synchronization Busy 1 1 read-only GAINCORR GAINCORR Synchronization Busy 8 1 read-only INPUTCTRL INPUTCTRL Synchronization Busy 2 1 read-only OFFSETCORR OFFSETCTRL Synchronization Busy 9 1 read-only SAMPCTRL SAMPCTRL Synchronization Busy 5 1 read-only SWRST SWRST Synchronization Busy 0 1 read-only SWTRIG SWTRG Synchronization Busy 10 1 read-only WINLT WINLT Synchronization Busy 6 1 read-only WINUT WINUT Synchronization Busy 7 1 read-only ADC_WINLT Window Monitor Lower Threshold 0xE 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 ADC_WINUT Window Monitor Upper Threshold 0x10 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 AVGCTRL Average Control 0xC 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xA CALIB Calibration 0x2C 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run During Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0x0 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 CTRLC Control C 0xA 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 3 1 DIFFMODE Differential Mode 0 1 DUALSEL Dual Mode Trigger Selection 12 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 FREERUN Free Running Mode 2 1 LEFTADJ Left-Adjusted Result 1 1 R2R Rail-to-Rail mode enable 7 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit 0x0 16BIT 16-bit averaging mode 0x1 10BIT 10-bit 0x2 8BIT 8-bit 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 DBGCTRL Debug Control 0x1C 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x3 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Start Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x12 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 INPUTCTRL Input Control 0x8 16 read-write n 0x0 0x0 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 GND Internal Ground 0x18 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1A SCALEDIOVCC 1/4 Scaled I/O Supply 0x1B DAC DAC Output 0x1C AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xA AIN11 ADC AIN11 Pin 0xB INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 OFFSETCORR Offset Correction 0x14 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x2 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 DAC DAC 0x4 INTVCC2 VDDANA 0x5 RESULT Result 0x24 16 read-only n 0x0 0x0 RESULT Result Value 0 16 read-only SAMPCTRL Sample Time Control 0xD 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 SEQCTRL Sequence Control 0x28 32 read-write n 0x0 0x0 SEQEN Enable Positive Input in the Sequence 0 32 SEQSTATUS Sequence Status 0x7 8 read-only n 0x0 0x0 SEQBUSY Sequence Busy 7 1 read-only SEQSTATE Sequence State 0 5 read-only SWTRIG Software Trigger 0x18 8 read-write n 0x0 0x0 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 SYNCBUSY Synchronization Busy 0x20 16 read-only n 0x0 0x0 AVGCTRL AVGCTRL Synchronization Busy 4 1 read-only CTRLC CTRLC Synchronization Busy 3 1 read-only ENABLE ENABLE Synchronization Busy 1 1 read-only GAINCORR GAINCORR Synchronization Busy 8 1 read-only INPUTCTRL INPUTCTRL Synchronization Busy 2 1 read-only OFFSETCORR OFFSETCTRL Synchronization Busy 9 1 read-only SAMPCTRL SAMPCTRL Synchronization Busy 5 1 read-only SWRST SWRST Synchronization Busy 0 1 read-only SWTRIG SWTRG Synchronization Busy 10 1 read-only WINLT WINLT Synchronization Busy 6 1 read-only WINUT WINUT Synchronization Busy 7 1 read-only WINLT Window Monitor Lower Threshold 0xE 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x10 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 CAN0 Control Area Network CAN 0x0 0x0 0x200 registers n 0x0 0xFC registers n CAN0_INTREQ 15 CAN0 15 CAN_CCCR CC Control 0x18 32 read-write n 0x0 0x0 ASM ASM Restricted Operation Mode 2 1 BRSE Bit Rate Switch Enable 9 1 CCE Configuration Change Enable 1 1 CSA Clock Stop Acknowledge 3 1 read-only CSR Clock Stop Request 4 1 DAR Disable Automatic Retransmission 6 1 EFBI Edge Filtering during Bus Integration 13 1 FDOE FD Operation Enable 8 1 INIT Initialization 0 1 MON Bus Monitoring Mode 5 1 NISO Non ISO Operation 15 1 PXHD Protocol Exception Handling Disable 12 1 TEST Test Mode Enable 7 1 TXP Transmit Pause 14 1 CAN_CREL Core Release 0x0 32 read-only n 0x0 0x0 REL Core Release 28 4 read-only STEP Step of Core Release 24 4 read-only SUBSTEP Sub-step of Core Release 20 4 read-only CAN_DBTP Fast Bit Timing and Prescaler 0xC 32 read-write n 0x0 0x0 DBRP Data Baud Rate Prescaler 16 5 DSJW Data (Re)Synchronization Jump Width 0 4 DTSEG1 Data time segment before sample point 8 5 DTSEG2 Data time segment after sample point 4 4 TDC Tranceiver Delay Compensation 23 1 CAN_ECR Error Counter 0x40 32 read-only n 0x0 0x0 CEL CAN Error Logging 16 8 read-only REC Receive Error Counter 8 7 read-only RP Receive Error Passive 15 1 read-only TEC Transmit Error Counter 0 8 read-only CAN_ENDN Endian 0x4 32 read-only n 0x0 0x0 ETV Endianness Test Value 0 32 read-only CAN_GFC Global Filter Configuration 0x80 32 read-write n 0x0 0x0 ANFE Accept Non-matching Frames Extended 2 2 ANFESelect RXF0 Accept in Rx FIFO 0 0x0 RXF1 Accept in Rx FIFO 1 0x1 REJECT Reject 0x2 ANFS Accept Non-matching Frames Standard 4 2 ANFSSelect RXF0 Accept in Rx FIFO 0 0x0 RXF1 Accept in Rx FIFO 1 0x1 REJECT Reject 0x2 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 CAN_HPMS High Priority Message Status 0x94 32 read-only n 0x0 0x0 BIDX Buffer Index 0 6 read-only FIDX Filter Index 8 7 read-only FLST Filter List 15 1 read-only MSI Message Storage Indicator 6 2 read-only MSISelect NONE No FIFO selected 0x0 LOST FIFO message lost 0x1 FIFO0 Message stored in FIFO 0 0x2 FIFO1 Message stored in FIFO 1 0x3 CAN_IE Interrupt Enable 0x54 32 read-write n 0x0 0x0 ARAE Access to Reserved Address Enable 29 1 BECE Bit Error Corrected Interrupt Enable 20 1 BEUE Bit Error Uncorrected Interrupt Enable 21 1 BOE Bus_Off Status Interrupt Enable 25 1 DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 1 ELOE Error Logging Overflow Interrupt Enable 22 1 EPE Error Passive Interrupt Enable 23 1 EWE Warning Status Interrupt Enable 24 1 HPME High Priority Message Interrupt Enable 8 1 MRAFE Message RAM Access Failure Interrupt Enable 17 1 PEAE Protocol Error in Arbitration Phase Enable 27 1 PEDE Protocol Error in Data Phase Enable 28 1 RF0FE Rx FIFO 0 Full Interrupt Enable 2 1 RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 1 RF0NE Rx FIFO 0 New Message Interrupt Enable 0 1 RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 RF1FE Rx FIFO 1 FIFO Full Interrupt Enable 6 1 RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 1 RF1NE Rx FIFO 1 New Message Interrupt Enable 4 1 RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 1 TCE Timestamp Completed Interrupt Enable 9 1 TCFE Transmission Cancellation Finished Interrupt Enable 10 1 TEFFE Tx Event FIFO Full Interrupt Enable 14 1 TEFLE Tx Event FIFO Element Lost Interrupt Enable 15 1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 TFEE Tx FIFO Empty Interrupt Enable 11 1 TOOE Timeout Occurred Interrupt Enable 18 1 TSWE Timestamp Wraparound Interrupt Enable 16 1 WDIE Watchdog Interrupt Interrupt Enable 26 1 CAN_ILE Interrupt Line Enable 0x5C 32 read-write n 0x0 0x0 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 CAN_ILS Interrupt Line Select 0x58 32 read-write n 0x0 0x0 ARAL Access to Reserved Address Line 29 1 BECL Bit Error Corrected Interrupt Line 20 1 BEUL Bit Error Uncorrected Interrupt Line 21 1 BOL Bus_Off Status Interrupt Line 25 1 DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 HPML High Priority Message Interrupt Line 8 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 PEAL Protocol Error in Arbitration Phase Line 27 1 PEDL Protocol Error in Data Phase Line 28 1 RF0FL Rx FIFO 0 Full Interrupt Line 2 1 RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 1 RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 RF1FL Rx FIFO 1 FIFO Full Interrupt Line 6 1 RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 1 RF1NL Rx FIFO 1 New Message Interrupt Line 4 1 RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TCL Timestamp Completed Interrupt Line 9 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Element Lost Interrupt Line 15 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TFEL Tx FIFO Empty Interrupt Line 11 1 TOOL Timeout Occurred Interrupt Line 18 1 TSWL Timestamp Wraparound Interrupt Line 16 1 WDIL Watchdog Interrupt Interrupt Line 26 1 CAN_IR Interrupt 0x50 32 read-write n 0x0 0x0 ARA Access to Reserved Address 29 1 BEC Bit Error Corrected 20 1 BEU Bit Error Uncorrected 21 1 BO Bus_Off Status 25 1 DRX Message stored to Dedicated Rx Buffer 19 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 HPM High Priority Message 8 1 MRAF Message RAM Access Failure 17 1 PEA Protocol Error in Arbitration Phase 27 1 PED Protocol Error in Data Phase 28 1 RF0F Rx FIFO 0 Full 2 1 RF0L Rx FIFO 0 Message Lost 3 1 RF0N Rx FIFO 0 New Message 0 1 RF0W Rx FIFO 0 Watermark Reached 1 1 RF1F Rx FIFO 1 FIFO Full 6 1 RF1L Rx FIFO 1 Message Lost 7 1 RF1N Rx FIFO 1 New Message 4 1 RF1W Rx FIFO 1 Watermark Reached 5 1 TC Timestamp Completed 9 1 TCF Transmission Cancellation Finished 10 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TFE Tx FIFO Empty 11 1 TOO Timeout Occurred 18 1 TSW Timestamp Wraparound 16 1 WDI Watchdog Interrupt 26 1 CAN_MRCFG Message RAM Configuration 0x8 32 read-write n 0x0 0x0 QOS Quality of Service 0 2 QOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 CAN_NBTP Nominal Bit Timing and Prescaler 0x1C 32 read-write n 0x0 0x0 NBRP Nominal Baud Rate Prescaler 16 9 NSJW Nominal (Re)Synchronization Jump Width 25 7 NTSEG1 Nominal Time segment before sample point 8 8 NTSEG2 Nominal Time segment after sample point 0 7 CAN_NDAT1 New Data 1 0x98 32 read-write n 0x0 0x0 ND0 New Data 0 0 1 ND1 New Data 1 1 1 ND10 New Data 10 10 1 ND11 New Data 11 11 1 ND12 New Data 12 12 1 ND13 New Data 13 13 1 ND14 New Data 14 14 1 ND15 New Data 15 15 1 ND16 New Data 16 16 1 ND17 New Data 17 17 1 ND18 New Data 18 18 1 ND19 New Data 19 19 1 ND2 New Data 2 2 1 ND20 New Data 20 20 1 ND21 New Data 21 21 1 ND22 New Data 22 22 1 ND23 New Data 23 23 1 ND24 New Data 24 24 1 ND25 New Data 25 25 1 ND26 New Data 26 26 1 ND27 New Data 27 27 1 ND28 New Data 28 28 1 ND29 New Data 29 29 1 ND3 New Data 3 3 1 ND30 New Data 30 30 1 ND31 New Data 31 31 1 ND4 New Data 4 4 1 ND5 New Data 5 5 1 ND6 New Data 6 6 1 ND7 New Data 7 7 1 ND8 New Data 8 8 1 ND9 New Data 9 9 1 CAN_NDAT2 New Data 2 0x9C 32 read-write n 0x0 0x0 ND32 New Data 32 0 1 ND33 New Data 33 1 1 ND34 New Data 34 2 1 ND35 New Data 35 3 1 ND36 New Data 36 4 1 ND37 New Data 37 5 1 ND38 New Data 38 6 1 ND39 New Data 39 7 1 ND40 New Data 40 8 1 ND41 New Data 41 9 1 ND42 New Data 42 10 1 ND43 New Data 43 11 1 ND44 New Data 44 12 1 ND45 New Data 45 13 1 ND46 New Data 46 14 1 ND47 New Data 47 15 1 ND48 New Data 48 16 1 ND49 New Data 49 17 1 ND50 New Data 50 18 1 ND51 New Data 51 19 1 ND52 New Data 52 20 1 ND53 New Data 53 21 1 ND54 New Data 54 22 1 ND55 New Data 55 23 1 ND56 New Data 56 24 1 ND57 New Data 57 25 1 ND58 New Data 58 26 1 ND59 New Data 59 27 1 ND60 New Data 60 28 1 ND61 New Data 61 29 1 ND62 New Data 62 30 1 ND63 New Data 63 31 1 CAN_PSR Protocol Status 0x44 32 read-only n 0x0 0x0 ACT Activity 3 2 read-only ACTSelect SYNC Node is synchronizing on CAN communication 0x0 IDLE Node is neither receiver nor transmitter 0x1 RX Node is operating as receiver 0x2 TX Node is operating as transmitter 0x3 BO Bus_Off Status 7 1 read-only DLEC Data Phase Last Error Code 8 3 read-only DLECSelect NONE No Error 0x0 STUFF Stuff Error 0x1 FORM Form Error 0x2 ACK Ack Error 0x3 BIT1 Bit1 Error 0x4 BIT0 Bit0 Error 0x5 CRC CRC Error 0x6 NC No Change 0x7 EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only LEC Last Error Code 0 3 read-only LECSelect NONE No Error 0x0 STUFF Stuff Error 0x1 FORM Form Error 0x2 ACK Ack Error 0x3 BIT1 Bit1 Error 0x4 BIT0 Bit0 Error 0x5 CRC CRC Error 0x6 NC No Change 0x7 PXE Protocol Exception Event 14 1 read-only RBRS BRS flag of last received CAN FD Message 12 1 read-only RESI ESI flag of last received CAN FD Message 11 1 read-only RFDF Received a CAN FD Message 13 1 read-only TDCV Transmitter Delay Compensation Value 16 7 read-only CAN_RWD RAM Watchdog 0x14 32 read-write n 0x0 0x0 WDC Watchdog Configuration 0 8 read-only WDV Watchdog Value 8 8 read-only CAN_RXBC Rx Buffer Configuration 0xAC 32 read-write n 0x0 0x0 RBSA Rx Buffer Start Address 0 16 CAN_RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write n 0x0 0x0 F0DS Rx FIFO 0 Data Field Size 0 3 F0DSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 F1DS Rx FIFO 1 Data Field Size 4 3 F1DSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 RBDS Rx Buffer Data Field Size 8 3 RBDSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 CAN_RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write n 0x0 0x0 F0AI Rx FIFO 0 Acknowledge Index 0 6 CAN_RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write n 0x0 0x0 F0OM FIFO 0 Operation Mode 31 1 F0S Rx FIFO 0 Size 16 7 F0SA Rx FIFO 0 Start Address 0 16 F0WM Rx FIFO 0 Watermark 24 7 CAN_RXF0S Rx FIFO 0 Status 0xA4 32 read-only n 0x0 0x0 F0F Rx FIFO 0 Full 24 1 read-only F0FL Rx FIFO 0 Fill Level 0 7 read-only F0GI Rx FIFO 0 Get Index 8 6 read-only F0PI Rx FIFO 0 Put Index 16 6 read-only RF0L Rx FIFO 0 Message Lost 25 1 read-only CAN_RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write n 0x0 0x0 F1AI Rx FIFO 1 Acknowledge Index 0 6 CAN_RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write n 0x0 0x0 F1OM FIFO 1 Operation Mode 31 1 F1S Rx FIFO 1 Size 16 7 F1SA Rx FIFO 1 Start Address 0 16 F1WM Rx FIFO 1 Watermark 24 7 CAN_RXF1S Rx FIFO 1 Status 0xB4 32 read-only n 0x0 0x0 DMS Debug Message Status 30 2 read-only DMSSelect IDLE Idle state 0x0 DBGA Debug message A received 0x1 DBGB Debug message A/B received 0x2 DBGC Debug message A/B/C received, DMA request set 0x3 F1F Rx FIFO 1 Full 24 1 read-only F1FL Rx FIFO 1 Fill Level 0 7 read-only F1GI Rx FIFO 1 Get Index 8 6 read-only F1PI Rx FIFO 1 Put Index 16 6 read-only RF1L Rx FIFO 1 Message Lost 25 1 read-only CAN_SIDFC Standard ID Filter Configuration 0x84 32 read-write n 0x0 0x0 FLSSA Filter List Standard Start Address 0 16 LSS List Size Standard 16 8 CAN_TDCR Extended ID Filter Configuration 0x48 32 read-write n 0x0 0x0 TDCF Transmitter Delay Compensation Filter Length 0 7 read-only TDCO Transmitter Delay Compensation Offset 8 7 CAN_TEST Test 0x10 32 read-write n 0x0 0x0 LBCK Loop Back Mode 4 1 RX Receive Pin 7 1 read-only TX Control of Transmit Pin 5 2 TXSelect CORE TX controlled by CAN core 0x0 SAMPLE TX monitoring sample point 0x1 DOMINANT Dominant (0) level at pin CAN_TX 0x2 RECESSIVE Recessive (1) level at pin CAN_TX 0x3 CAN_TOCC Timeout Counter Configuration 0x28 32 read-write n 0x0 0x0 ETOC Enable Timeout Counter 0 1 TOP Timeout Period 16 16 TOS Timeout Select 1 2 TOSSelect CONT Continuout operation 0x0 TXEF Timeout controlled by TX Event FIFO 0x1 RXF0 Timeout controlled by Rx FIFO 0 0x2 RXF1 Timeout controlled by Rx FIFO 1 0x3 CAN_TOCV Timeout Counter Value 0x2C 32 read-write n 0x0 0x0 TOC Timeout Counter 0 16 CAN_TSCC Timestamp Counter Configuration 0x20 32 read-write n 0x0 0x0 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSSSelect ZERO Timestamp counter value always 0x0000 0x0 INC Timestamp counter value incremented by TCP 0x1 EXT External timestamp counter value used 0x2 CAN_TSCV Timestamp Counter Value 0x24 32 read-only n 0x0 0x0 TSC Timestamp Counter 0 16 read-only CAN_TXBAR Tx Buffer Add Request 0xD0 32 read-write n 0x0 0x0 AR0 Add Request 0 0 1 AR1 Add Request 1 1 1 AR10 Add Request 10 10 1 AR11 Add Request 11 11 1 AR12 Add Request 12 12 1 AR13 Add Request 13 13 1 AR14 Add Request 14 14 1 AR15 Add Request 15 15 1 AR16 Add Request 16 16 1 AR17 Add Request 17 17 1 AR18 Add Request 18 18 1 AR19 Add Request 19 19 1 AR2 Add Request 2 2 1 AR20 Add Request 20 20 1 AR21 Add Request 21 21 1 AR22 Add Request 22 22 1 AR23 Add Request 23 23 1 AR24 Add Request 24 24 1 AR25 Add Request 25 25 1 AR26 Add Request 26 26 1 AR27 Add Request 27 27 1 AR28 Add Request 28 28 1 AR29 Add Request 29 29 1 AR3 Add Request 3 3 1 AR30 Add Request 30 30 1 AR31 Add Request 31 31 1 AR4 Add Request 4 4 1 AR5 Add Request 5 5 1 AR6 Add Request 6 6 1 AR7 Add Request 7 7 1 AR8 Add Request 8 8 1 AR9 Add Request 9 9 1 CAN_TXBC Tx Buffer Configuration 0xC0 32 read-write n 0x0 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 TBSA Tx Buffers Start Address 0 16 TFQM Tx FIFO/Queue Mode 30 1 TFQS Transmit FIFO/Queue Size 24 6 CAN_TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only n 0x0 0x0 CF0 Tx Buffer Cancellation Finished 0 0 1 read-only CF1 Tx Buffer Cancellation Finished 1 1 1 read-only CF10 Tx Buffer Cancellation Finished 10 10 1 read-only CF11 Tx Buffer Cancellation Finished 11 11 1 read-only CF12 Tx Buffer Cancellation Finished 12 12 1 read-only CF13 Tx Buffer Cancellation Finished 13 13 1 read-only CF14 Tx Buffer Cancellation Finished 14 14 1 read-only CF15 Tx Buffer Cancellation Finished 15 15 1 read-only CF16 Tx Buffer Cancellation Finished 16 16 1 read-only CF17 Tx Buffer Cancellation Finished 17 17 1 read-only CF18 Tx Buffer Cancellation Finished 18 18 1 read-only CF19 Tx Buffer Cancellation Finished 19 19 1 read-only CF2 Tx Buffer Cancellation Finished 2 2 1 read-only CF20 Tx Buffer Cancellation Finished 20 20 1 read-only CF21 Tx Buffer Cancellation Finished 21 21 1 read-only CF22 Tx Buffer Cancellation Finished 22 22 1 read-only CF23 Tx Buffer Cancellation Finished 23 23 1 read-only CF24 Tx Buffer Cancellation Finished 24 24 1 read-only CF25 Tx Buffer Cancellation Finished 25 25 1 read-only CF26 Tx Buffer Cancellation Finished 26 26 1 read-only CF27 Tx Buffer Cancellation Finished 27 27 1 read-only CF28 Tx Buffer Cancellation Finished 28 28 1 read-only CF29 Tx Buffer Cancellation Finished 29 29 1 read-only CF3 Tx Buffer Cancellation Finished 3 3 1 read-only CF30 Tx Buffer Cancellation Finished 30 30 1 read-only CF31 Tx Buffer Cancellation Finished 31 31 1 read-only CF4 Tx Buffer Cancellation Finished 4 4 1 read-only CF5 Tx Buffer Cancellation Finished 5 5 1 read-only CF6 Tx Buffer Cancellation Finished 6 6 1 read-only CF7 Tx Buffer Cancellation Finished 7 7 1 read-only CF8 Tx Buffer Cancellation Finished 8 8 1 read-only CF9 Tx Buffer Cancellation Finished 9 9 1 read-only CAN_TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write n 0x0 0x0 CFIE0 Cancellation Finished Interrupt Enable 0 0 1 CFIE1 Cancellation Finished Interrupt Enable 1 1 1 CFIE10 Cancellation Finished Interrupt Enable 10 10 1 CFIE11 Cancellation Finished Interrupt Enable 11 11 1 CFIE12 Cancellation Finished Interrupt Enable 12 12 1 CFIE13 Cancellation Finished Interrupt Enable 13 13 1 CFIE14 Cancellation Finished Interrupt Enable 14 14 1 CFIE15 Cancellation Finished Interrupt Enable 15 15 1 CFIE16 Cancellation Finished Interrupt Enable 16 16 1 CFIE17 Cancellation Finished Interrupt Enable 17 17 1 CFIE18 Cancellation Finished Interrupt Enable 18 18 1 CFIE19 Cancellation Finished Interrupt Enable 19 19 1 CFIE2 Cancellation Finished Interrupt Enable 2 2 1 CFIE20 Cancellation Finished Interrupt Enable 20 20 1 CFIE21 Cancellation Finished Interrupt Enable 21 21 1 CFIE22 Cancellation Finished Interrupt Enable 22 22 1 CFIE23 Cancellation Finished Interrupt Enable 23 23 1 CFIE24 Cancellation Finished Interrupt Enable 24 24 1 CFIE25 Cancellation Finished Interrupt Enable 25 25 1 CFIE26 Cancellation Finished Interrupt Enable 26 26 1 CFIE27 Cancellation Finished Interrupt Enable 27 27 1 CFIE28 Cancellation Finished Interrupt Enable 28 28 1 CFIE29 Cancellation Finished Interrupt Enable 29 29 1 CFIE3 Cancellation Finished Interrupt Enable 3 3 1 CFIE30 Cancellation Finished Interrupt Enable 30 30 1 CFIE31 Cancellation Finished Interrupt Enable 31 31 1 CFIE4 Cancellation Finished Interrupt Enable 4 4 1 CFIE5 Cancellation Finished Interrupt Enable 5 5 1 CFIE6 Cancellation Finished Interrupt Enable 6 6 1 CFIE7 Cancellation Finished Interrupt Enable 7 7 1 CFIE8 Cancellation Finished Interrupt Enable 8 8 1 CFIE9 Cancellation Finished Interrupt Enable 9 9 1 CAN_TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write n 0x0 0x0 CR0 Cancellation Request 0 0 1 CR1 Cancellation Request 1 1 1 CR10 Cancellation Request 10 10 1 CR11 Cancellation Request 11 11 1 CR12 Cancellation Request 12 12 1 CR13 Cancellation Request 13 13 1 CR14 Cancellation Request 14 14 1 CR15 Cancellation Request 15 15 1 CR16 Cancellation Request 16 16 1 CR17 Cancellation Request 17 17 1 CR18 Cancellation Request 18 18 1 CR19 Cancellation Request 19 19 1 CR2 Cancellation Request 2 2 1 CR20 Cancellation Request 20 20 1 CR21 Cancellation Request 21 21 1 CR22 Cancellation Request 22 22 1 CR23 Cancellation Request 23 23 1 CR24 Cancellation Request 24 24 1 CR25 Cancellation Request 25 25 1 CR26 Cancellation Request 26 26 1 CR27 Cancellation Request 27 27 1 CR28 Cancellation Request 28 28 1 CR29 Cancellation Request 29 29 1 CR3 Cancellation Request 3 3 1 CR30 Cancellation Request 30 30 1 CR31 Cancellation Request 31 31 1 CR4 Cancellation Request 4 4 1 CR5 Cancellation Request 5 5 1 CR6 Cancellation Request 6 6 1 CR7 Cancellation Request 7 7 1 CR8 Cancellation Request 8 8 1 CR9 Cancellation Request 9 9 1 CAN_TXBRP Tx Buffer Request Pending 0xCC 32 read-only n 0x0 0x0 TRP0 Transmission Request Pending 0 0 1 read-only TRP1 Transmission Request Pending 1 1 1 read-only TRP10 Transmission Request Pending 10 10 1 read-only TRP11 Transmission Request Pending 11 11 1 read-only TRP12 Transmission Request Pending 12 12 1 read-only TRP13 Transmission Request Pending 13 13 1 read-only TRP14 Transmission Request Pending 14 14 1 read-only TRP15 Transmission Request Pending 15 15 1 read-only TRP16 Transmission Request Pending 16 16 1 read-only TRP17 Transmission Request Pending 17 17 1 read-only TRP18 Transmission Request Pending 18 18 1 read-only TRP19 Transmission Request Pending 19 19 1 read-only TRP2 Transmission Request Pending 2 2 1 read-only TRP20 Transmission Request Pending 20 20 1 read-only TRP21 Transmission Request Pending 21 21 1 read-only TRP22 Transmission Request Pending 22 22 1 read-only TRP23 Transmission Request Pending 23 23 1 read-only TRP24 Transmission Request Pending 24 24 1 read-only TRP25 Transmission Request Pending 25 25 1 read-only TRP26 Transmission Request Pending 26 26 1 read-only TRP27 Transmission Request Pending 27 27 1 read-only TRP28 Transmission Request Pending 28 28 1 read-only TRP29 Transmission Request Pending 29 29 1 read-only TRP3 Transmission Request Pending 3 3 1 read-only TRP30 Transmission Request Pending 30 30 1 read-only TRP31 Transmission Request Pending 31 31 1 read-only TRP4 Transmission Request Pending 4 4 1 read-only TRP5 Transmission Request Pending 5 5 1 read-only TRP6 Transmission Request Pending 6 6 1 read-only TRP7 Transmission Request Pending 7 7 1 read-only TRP8 Transmission Request Pending 8 8 1 read-only TRP9 Transmission Request Pending 9 9 1 read-only CAN_TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write n 0x0 0x0 TIE0 Transmission Interrupt Enable 0 0 1 TIE1 Transmission Interrupt Enable 1 1 1 TIE10 Transmission Interrupt Enable 10 10 1 TIE11 Transmission Interrupt Enable 11 11 1 TIE12 Transmission Interrupt Enable 12 12 1 TIE13 Transmission Interrupt Enable 13 13 1 TIE14 Transmission Interrupt Enable 14 14 1 TIE15 Transmission Interrupt Enable 15 15 1 TIE16 Transmission Interrupt Enable 16 16 1 TIE17 Transmission Interrupt Enable 17 17 1 TIE18 Transmission Interrupt Enable 18 18 1 TIE19 Transmission Interrupt Enable 19 19 1 TIE2 Transmission Interrupt Enable 2 2 1 TIE20 Transmission Interrupt Enable 20 20 1 TIE21 Transmission Interrupt Enable 21 21 1 TIE22 Transmission Interrupt Enable 22 22 1 TIE23 Transmission Interrupt Enable 23 23 1 TIE24 Transmission Interrupt Enable 24 24 1 TIE25 Transmission Interrupt Enable 25 25 1 TIE26 Transmission Interrupt Enable 26 26 1 TIE27 Transmission Interrupt Enable 27 27 1 TIE28 Transmission Interrupt Enable 28 28 1 TIE29 Transmission Interrupt Enable 29 29 1 TIE3 Transmission Interrupt Enable 3 3 1 TIE30 Transmission Interrupt Enable 30 30 1 TIE31 Transmission Interrupt Enable 31 31 1 TIE4 Transmission Interrupt Enable 4 4 1 TIE5 Transmission Interrupt Enable 5 5 1 TIE6 Transmission Interrupt Enable 6 6 1 TIE7 Transmission Interrupt Enable 7 7 1 TIE8 Transmission Interrupt Enable 8 8 1 TIE9 Transmission Interrupt Enable 9 9 1 CAN_TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only n 0x0 0x0 TO0 Transmission Occurred 0 0 1 read-only TO1 Transmission Occurred 1 1 1 read-only TO10 Transmission Occurred 10 10 1 read-only TO11 Transmission Occurred 11 11 1 read-only TO12 Transmission Occurred 12 12 1 read-only TO13 Transmission Occurred 13 13 1 read-only TO14 Transmission Occurred 14 14 1 read-only TO15 Transmission Occurred 15 15 1 read-only TO16 Transmission Occurred 16 16 1 read-only TO17 Transmission Occurred 17 17 1 read-only TO18 Transmission Occurred 18 18 1 read-only TO19 Transmission Occurred 19 19 1 read-only TO2 Transmission Occurred 2 2 1 read-only TO20 Transmission Occurred 20 20 1 read-only TO21 Transmission Occurred 21 21 1 read-only TO22 Transmission Occurred 22 22 1 read-only TO23 Transmission Occurred 23 23 1 read-only TO24 Transmission Occurred 24 24 1 read-only TO25 Transmission Occurred 25 25 1 read-only TO26 Transmission Occurred 26 26 1 read-only TO27 Transmission Occurred 27 27 1 read-only TO28 Transmission Occurred 28 28 1 read-only TO29 Transmission Occurred 29 29 1 read-only TO3 Transmission Occurred 3 3 1 read-only TO30 Transmission Occurred 30 30 1 read-only TO31 Transmission Occurred 31 31 1 read-only TO4 Transmission Occurred 4 4 1 read-only TO5 Transmission Occurred 5 5 1 read-only TO6 Transmission Occurred 6 6 1 read-only TO7 Transmission Occurred 7 7 1 read-only TO8 Transmission Occurred 8 8 1 read-only TO9 Transmission Occurred 9 9 1 read-only CAN_TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write n 0x0 0x0 EFAI Event FIFO Acknowledge Index 0 5 CAN_TXEFC Tx Event FIFO Configuration 0xF0 32 read-write n 0x0 0x0 EFS Event FIFO Size 16 6 EFSA Event FIFO Start Address 0 16 EFWM Event FIFO Watermark 24 6 CAN_TXEFS Tx Event FIFO Status 0xF4 32 read-only n 0x0 0x0 EFF Event FIFO Full 24 1 read-only EFFL Event FIFO Fill Level 0 6 read-only EFGI Event FIFO Get Index 8 5 read-only EFPI Event FIFO Put Index 16 5 read-only TEFL Tx Event FIFO Element Lost 25 1 read-only CAN_TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write n 0x0 0x0 TBDS Tx Buffer Data Field Size 0 3 TBDSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 CAN_TXFQS Tx FIFO / Queue Status 0xC4 32 read-only n 0x0 0x0 TFFL Tx FIFO Free Level 0 6 read-only TFGI Tx FIFO Get Index 8 5 read-only TFQF Tx FIFO/Queue Full 21 1 read-only TFQPI Tx FIFO/Queue Put Index 16 5 read-only CAN_XIDAM Extended ID AND Mask 0x90 32 read-write n 0x0 0x0 EIDM Extended ID Mask 0 29 CAN_XIDFC Extended ID Filter Configuration 0x88 32 read-write n 0x0 0x0 FLESA Filter List Extended Start Address 0 16 LSE List Size Extended 16 7 CCCR CC Control 0x18 32 read-write n 0x0 0x0 ASM ASM Restricted Operation Mode 2 1 BRSE Bit Rate Switch Enable 9 1 CCE Configuration Change Enable 1 1 CSA Clock Stop Acknowledge 3 1 read-only CSR Clock Stop Request 4 1 DAR Disable Automatic Retransmission 6 1 EFBI Edge Filtering during Bus Integration 13 1 FDOE FD Operation Enable 8 1 INIT Initialization 0 1 MON Bus Monitoring Mode 5 1 NISO Non ISO Operation 15 1 PXHD Protocol Exception Handling Disable 12 1 TEST Test Mode Enable 7 1 TXP Transmit Pause 14 1 CREL Core Release 0x0 32 read-only n 0x0 0x0 REL Core Release 28 4 read-only STEP Step of Core Release 24 4 read-only SUBSTEP Sub-step of Core Release 20 4 read-only DBTP Fast Bit Timing and Prescaler 0xC 32 read-write n 0x0 0x0 DBRP Data Baud Rate Prescaler 16 5 DSJW Data (Re)Synchronization Jump Width 0 4 DTSEG1 Data time segment before sample point 8 5 DTSEG2 Data time segment after sample point 4 4 TDC Tranceiver Delay Compensation 23 1 ECR Error Counter 0x40 32 read-only n 0x0 0x0 CEL CAN Error Logging 16 8 read-only REC Receive Error Counter 8 7 read-only RP Receive Error Passive 15 1 read-only TEC Transmit Error Counter 0 8 read-only ENDN Endian 0x4 32 read-only n 0x0 0x0 ETV Endianness Test Value 0 32 read-only GFC Global Filter Configuration 0x80 32 read-write n 0x0 0x0 ANFE Accept Non-matching Frames Extended 2 2 ANFESelect RXF0 Accept in Rx FIFO 0 0 RXF1 Accept in Rx FIFO 1 1 REJECT Reject 2 ANFS Accept Non-matching Frames Standard 4 2 ANFSSelect RXF0 Accept in Rx FIFO 0 0 RXF1 Accept in Rx FIFO 1 1 REJECT Reject 2 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 HPMS High Priority Message Status 0x94 32 read-only n 0x0 0x0 BIDX Buffer Index 0 6 read-only FIDX Filter Index 8 7 read-only FLST Filter List 15 1 read-only MSI Message Storage Indicator 6 2 read-only MSISelect NONE No FIFO selected 0 LOST FIFO message lost 1 FIFO0 Message stored in FIFO 0 2 FIFO1 Message stored in FIFO 1 3 IE Interrupt Enable 0x54 32 read-write n 0x0 0x0 ARAE Access to Reserved Address Enable 29 1 BECE Bit Error Corrected Interrupt Enable 20 1 BEUE Bit Error Uncorrected Interrupt Enable 21 1 BOE Bus_Off Status Interrupt Enable 25 1 DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 1 ELOE Error Logging Overflow Interrupt Enable 22 1 EPE Error Passive Interrupt Enable 23 1 EWE Warning Status Interrupt Enable 24 1 HPME High Priority Message Interrupt Enable 8 1 MRAFE Message RAM Access Failure Interrupt Enable 17 1 PEAE Protocol Error in Arbitration Phase Enable 27 1 PEDE Protocol Error in Data Phase Enable 28 1 RF0FE Rx FIFO 0 Full Interrupt Enable 2 1 RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 1 RF0NE Rx FIFO 0 New Message Interrupt Enable 0 1 RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 RF1FE Rx FIFO 1 FIFO Full Interrupt Enable 6 1 RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 1 RF1NE Rx FIFO 1 New Message Interrupt Enable 4 1 RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 1 TCE Timestamp Completed Interrupt Enable 9 1 TCFE Transmission Cancellation Finished Interrupt Enable 10 1 TEFFE Tx Event FIFO Full Interrupt Enable 14 1 TEFLE Tx Event FIFO Element Lost Interrupt Enable 15 1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 TFEE Tx FIFO Empty Interrupt Enable 11 1 TOOE Timeout Occurred Interrupt Enable 18 1 TSWE Timestamp Wraparound Interrupt Enable 16 1 WDIE Watchdog Interrupt Interrupt Enable 26 1 ILE Interrupt Line Enable 0x5C 32 read-write n 0x0 0x0 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 ILS Interrupt Line Select 0x58 32 read-write n 0x0 0x0 ARAL Access to Reserved Address Line 29 1 BECL Bit Error Corrected Interrupt Line 20 1 BEUL Bit Error Uncorrected Interrupt Line 21 1 BOL Bus_Off Status Interrupt Line 25 1 DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 HPML High Priority Message Interrupt Line 8 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 PEAL Protocol Error in Arbitration Phase Line 27 1 PEDL Protocol Error in Data Phase Line 28 1 RF0FL Rx FIFO 0 Full Interrupt Line 2 1 RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 1 RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 RF1FL Rx FIFO 1 FIFO Full Interrupt Line 6 1 RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 1 RF1NL Rx FIFO 1 New Message Interrupt Line 4 1 RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TCL Timestamp Completed Interrupt Line 9 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Element Lost Interrupt Line 15 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TFEL Tx FIFO Empty Interrupt Line 11 1 TOOL Timeout Occurred Interrupt Line 18 1 TSWL Timestamp Wraparound Interrupt Line 16 1 WDIL Watchdog Interrupt Interrupt Line 26 1 IR Interrupt 0x50 32 read-write n 0x0 0x0 ARA Access to Reserved Address 29 1 BEC Bit Error Corrected 20 1 BEU Bit Error Uncorrected 21 1 BO Bus_Off Status 25 1 DRX Message stored to Dedicated Rx Buffer 19 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 HPM High Priority Message 8 1 MRAF Message RAM Access Failure 17 1 PEA Protocol Error in Arbitration Phase 27 1 PED Protocol Error in Data Phase 28 1 RF0F Rx FIFO 0 Full 2 1 RF0L Rx FIFO 0 Message Lost 3 1 RF0N Rx FIFO 0 New Message 0 1 RF0W Rx FIFO 0 Watermark Reached 1 1 RF1F Rx FIFO 1 FIFO Full 6 1 RF1L Rx FIFO 1 Message Lost 7 1 RF1N Rx FIFO 1 New Message 4 1 RF1W Rx FIFO 1 Watermark Reached 5 1 TC Timestamp Completed 9 1 TCF Transmission Cancellation Finished 10 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TFE Tx FIFO Empty 11 1 TOO Timeout Occurred 18 1 TSW Timestamp Wraparound 16 1 WDI Watchdog Interrupt 26 1 MRCFG Message RAM Configuration 0x8 32 read-write n 0x0 0x0 QOS Quality of Service 0 2 QOSSelect DISABLE Background (no sensitive operation) 0 LOW Sensitive Bandwidth 1 MEDIUM Sensitive Latency 2 HIGH Critical Latency 3 NBTP Nominal Bit Timing and Prescaler 0x1C 32 read-write n 0x0 0x0 NBRP Nominal Baud Rate Prescaler 16 9 NSJW Nominal (Re)Synchronization Jump Width 25 7 NTSEG1 Nominal Time segment before sample point 8 8 NTSEG2 Nominal Time segment after sample point 0 7 NDAT1 New Data 1 0x98 32 read-write n 0x0 0x0 ND0 New Data 0 0 1 ND1 New Data 1 1 1 ND10 New Data 10 10 1 ND11 New Data 11 11 1 ND12 New Data 12 12 1 ND13 New Data 13 13 1 ND14 New Data 14 14 1 ND15 New Data 15 15 1 ND16 New Data 16 16 1 ND17 New Data 17 17 1 ND18 New Data 18 18 1 ND19 New Data 19 19 1 ND2 New Data 2 2 1 ND20 New Data 20 20 1 ND21 New Data 21 21 1 ND22 New Data 22 22 1 ND23 New Data 23 23 1 ND24 New Data 24 24 1 ND25 New Data 25 25 1 ND26 New Data 26 26 1 ND27 New Data 27 27 1 ND28 New Data 28 28 1 ND29 New Data 29 29 1 ND3 New Data 3 3 1 ND30 New Data 30 30 1 ND31 New Data 31 31 1 ND4 New Data 4 4 1 ND5 New Data 5 5 1 ND6 New Data 6 6 1 ND7 New Data 7 7 1 ND8 New Data 8 8 1 ND9 New Data 9 9 1 NDAT2 New Data 2 0x9C 32 read-write n 0x0 0x0 ND32 New Data 32 0 1 ND33 New Data 33 1 1 ND34 New Data 34 2 1 ND35 New Data 35 3 1 ND36 New Data 36 4 1 ND37 New Data 37 5 1 ND38 New Data 38 6 1 ND39 New Data 39 7 1 ND40 New Data 40 8 1 ND41 New Data 41 9 1 ND42 New Data 42 10 1 ND43 New Data 43 11 1 ND44 New Data 44 12 1 ND45 New Data 45 13 1 ND46 New Data 46 14 1 ND47 New Data 47 15 1 ND48 New Data 48 16 1 ND49 New Data 49 17 1 ND50 New Data 50 18 1 ND51 New Data 51 19 1 ND52 New Data 52 20 1 ND53 New Data 53 21 1 ND54 New Data 54 22 1 ND55 New Data 55 23 1 ND56 New Data 56 24 1 ND57 New Data 57 25 1 ND58 New Data 58 26 1 ND59 New Data 59 27 1 ND60 New Data 60 28 1 ND61 New Data 61 29 1 ND62 New Data 62 30 1 ND63 New Data 63 31 1 PSR Protocol Status 0x44 32 read-only n 0x0 0x0 ACT Activity 3 2 read-only ACTSelect SYNC Node is synchronizing on CAN communication 0 IDLE Node is neither receiver nor transmitter 1 RX Node is operating as receiver 2 TX Node is operating as transmitter 3 BO Bus_Off Status 7 1 read-only DLEC Data Phase Last Error Code 8 3 read-only DLECSelect NONE No Error 0 STUFF Stuff Error 1 FORM Form Error 2 ACK Ack Error 3 BIT1 Bit1 Error 4 BIT0 Bit0 Error 5 CRC CRC Error 6 NC No Change 7 EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only LEC Last Error Code 0 3 read-only LECSelect NONE No Error 0 STUFF Stuff Error 1 FORM Form Error 2 ACK Ack Error 3 BIT1 Bit1 Error 4 BIT0 Bit0 Error 5 CRC CRC Error 6 NC No Change 7 PXE Protocol Exception Event 14 1 read-only RBRS BRS flag of last received CAN FD Message 12 1 read-only RESI ESI flag of last received CAN FD Message 11 1 read-only RFDF Received a CAN FD Message 13 1 read-only TDCV Transmitter Delay Compensation Value 16 7 read-only RWD RAM Watchdog 0x14 32 read-write n 0x0 0x0 WDC Watchdog Configuration 0 8 read-only WDV Watchdog Value 8 8 read-only RXBC Rx Buffer Configuration 0xAC 32 read-write n 0x0 0x0 RBSA Rx Buffer Start Address 0 16 RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write n 0x0 0x0 F0DS Rx FIFO 0 Data Field Size 0 3 F0DSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 F1DS Rx FIFO 1 Data Field Size 4 3 F1DSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 RBDS Rx Buffer Data Field Size 8 3 RBDSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write n 0x0 0x0 F0AI Rx FIFO 0 Acknowledge Index 0 6 RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write n 0x0 0x0 F0OM FIFO 0 Operation Mode 31 1 F0S Rx FIFO 0 Size 16 7 F0SA Rx FIFO 0 Start Address 0 16 F0WM Rx FIFO 0 Watermark 24 7 RXF0S Rx FIFO 0 Status 0xA4 32 read-only n 0x0 0x0 F0F Rx FIFO 0 Full 24 1 read-only F0FL Rx FIFO 0 Fill Level 0 7 read-only F0GI Rx FIFO 0 Get Index 8 6 read-only F0PI Rx FIFO 0 Put Index 16 6 read-only RF0L Rx FIFO 0 Message Lost 25 1 read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write n 0x0 0x0 F1AI Rx FIFO 1 Acknowledge Index 0 6 RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write n 0x0 0x0 F1OM FIFO 1 Operation Mode 31 1 F1S Rx FIFO 1 Size 16 7 F1SA Rx FIFO 1 Start Address 0 16 F1WM Rx FIFO 1 Watermark 24 7 RXF1S Rx FIFO 1 Status 0xB4 32 read-only n 0x0 0x0 DMS Debug Message Status 30 2 read-only DMSSelect IDLE Idle state 0 DBGA Debug message A received 1 DBGB Debug message A/B received 2 DBGC Debug message A/B/C received, DMA request set 3 F1F Rx FIFO 1 Full 24 1 read-only F1FL Rx FIFO 1 Fill Level 0 7 read-only F1GI Rx FIFO 1 Get Index 8 6 read-only F1PI Rx FIFO 1 Put Index 16 6 read-only RF1L Rx FIFO 1 Message Lost 25 1 read-only SIDFC Standard ID Filter Configuration 0x84 32 read-write n 0x0 0x0 FLSSA Filter List Standard Start Address 0 16 LSS List Size Standard 16 8 TDCR Extended ID Filter Configuration 0x48 32 read-write n 0x0 0x0 TDCF Transmitter Delay Compensation Filter Length 0 7 read-only TDCO Transmitter Delay Compensation Offset 8 7 TEST Test 0x10 32 read-write n 0x0 0x0 LBCK Loop Back Mode 4 1 RX Receive Pin 7 1 read-only TX Control of Transmit Pin 5 2 TXSelect CORE TX controlled by CAN core 0 SAMPLE TX monitoring sample point 1 DOMINANT Dominant (0) level at pin CAN_TX 2 RECESSIVE Recessive (1) level at pin CAN_TX 3 TOCC Timeout Counter Configuration 0x28 32 read-write n 0x0 0x0 ETOC Enable Timeout Counter 0 1 TOP Timeout Period 16 16 TOS Timeout Select 1 2 TOSSelect CONT Continuout operation 0 TXEF Timeout controlled by TX Event FIFO 1 RXF0 Timeout controlled by Rx FIFO 0 2 RXF1 Timeout controlled by Rx FIFO 1 3 TOCV Timeout Counter Value 0x2C 32 read-write n 0x0 0x0 TOC Timeout Counter 0 16 TSCC Timestamp Counter Configuration 0x20 32 read-write n 0x0 0x0 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSSSelect ZERO Timestamp counter value always 0x0000 0 INC Timestamp counter value incremented by TCP 1 EXT External timestamp counter value used 2 TSCV Timestamp Counter Value 0x24 32 read-only n 0x0 0x0 TSC Timestamp Counter 0 16 read-only TXBAR Tx Buffer Add Request 0xD0 32 read-write n 0x0 0x0 AR0 Add Request 0 0 1 AR1 Add Request 1 1 1 AR10 Add Request 10 10 1 AR11 Add Request 11 11 1 AR12 Add Request 12 12 1 AR13 Add Request 13 13 1 AR14 Add Request 14 14 1 AR15 Add Request 15 15 1 AR16 Add Request 16 16 1 AR17 Add Request 17 17 1 AR18 Add Request 18 18 1 AR19 Add Request 19 19 1 AR2 Add Request 2 2 1 AR20 Add Request 20 20 1 AR21 Add Request 21 21 1 AR22 Add Request 22 22 1 AR23 Add Request 23 23 1 AR24 Add Request 24 24 1 AR25 Add Request 25 25 1 AR26 Add Request 26 26 1 AR27 Add Request 27 27 1 AR28 Add Request 28 28 1 AR29 Add Request 29 29 1 AR3 Add Request 3 3 1 AR30 Add Request 30 30 1 AR31 Add Request 31 31 1 AR4 Add Request 4 4 1 AR5 Add Request 5 5 1 AR6 Add Request 6 6 1 AR7 Add Request 7 7 1 AR8 Add Request 8 8 1 AR9 Add Request 9 9 1 TXBC Tx Buffer Configuration 0xC0 32 read-write n 0x0 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 TBSA Tx Buffers Start Address 0 16 TFQM Tx FIFO/Queue Mode 30 1 TFQS Transmit FIFO/Queue Size 24 6 TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only n 0x0 0x0 CF0 Tx Buffer Cancellation Finished 0 0 1 read-only CF1 Tx Buffer Cancellation Finished 1 1 1 read-only CF10 Tx Buffer Cancellation Finished 10 10 1 read-only CF11 Tx Buffer Cancellation Finished 11 11 1 read-only CF12 Tx Buffer Cancellation Finished 12 12 1 read-only CF13 Tx Buffer Cancellation Finished 13 13 1 read-only CF14 Tx Buffer Cancellation Finished 14 14 1 read-only CF15 Tx Buffer Cancellation Finished 15 15 1 read-only CF16 Tx Buffer Cancellation Finished 16 16 1 read-only CF17 Tx Buffer Cancellation Finished 17 17 1 read-only CF18 Tx Buffer Cancellation Finished 18 18 1 read-only CF19 Tx Buffer Cancellation Finished 19 19 1 read-only CF2 Tx Buffer Cancellation Finished 2 2 1 read-only CF20 Tx Buffer Cancellation Finished 20 20 1 read-only CF21 Tx Buffer Cancellation Finished 21 21 1 read-only CF22 Tx Buffer Cancellation Finished 22 22 1 read-only CF23 Tx Buffer Cancellation Finished 23 23 1 read-only CF24 Tx Buffer Cancellation Finished 24 24 1 read-only CF25 Tx Buffer Cancellation Finished 25 25 1 read-only CF26 Tx Buffer Cancellation Finished 26 26 1 read-only CF27 Tx Buffer Cancellation Finished 27 27 1 read-only CF28 Tx Buffer Cancellation Finished 28 28 1 read-only CF29 Tx Buffer Cancellation Finished 29 29 1 read-only CF3 Tx Buffer Cancellation Finished 3 3 1 read-only CF30 Tx Buffer Cancellation Finished 30 30 1 read-only CF31 Tx Buffer Cancellation Finished 31 31 1 read-only CF4 Tx Buffer Cancellation Finished 4 4 1 read-only CF5 Tx Buffer Cancellation Finished 5 5 1 read-only CF6 Tx Buffer Cancellation Finished 6 6 1 read-only CF7 Tx Buffer Cancellation Finished 7 7 1 read-only CF8 Tx Buffer Cancellation Finished 8 8 1 read-only CF9 Tx Buffer Cancellation Finished 9 9 1 read-only TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write n 0x0 0x0 CFIE0 Cancellation Finished Interrupt Enable 0 0 1 CFIE1 Cancellation Finished Interrupt Enable 1 1 1 CFIE10 Cancellation Finished Interrupt Enable 10 10 1 CFIE11 Cancellation Finished Interrupt Enable 11 11 1 CFIE12 Cancellation Finished Interrupt Enable 12 12 1 CFIE13 Cancellation Finished Interrupt Enable 13 13 1 CFIE14 Cancellation Finished Interrupt Enable 14 14 1 CFIE15 Cancellation Finished Interrupt Enable 15 15 1 CFIE16 Cancellation Finished Interrupt Enable 16 16 1 CFIE17 Cancellation Finished Interrupt Enable 17 17 1 CFIE18 Cancellation Finished Interrupt Enable 18 18 1 CFIE19 Cancellation Finished Interrupt Enable 19 19 1 CFIE2 Cancellation Finished Interrupt Enable 2 2 1 CFIE20 Cancellation Finished Interrupt Enable 20 20 1 CFIE21 Cancellation Finished Interrupt Enable 21 21 1 CFIE22 Cancellation Finished Interrupt Enable 22 22 1 CFIE23 Cancellation Finished Interrupt Enable 23 23 1 CFIE24 Cancellation Finished Interrupt Enable 24 24 1 CFIE25 Cancellation Finished Interrupt Enable 25 25 1 CFIE26 Cancellation Finished Interrupt Enable 26 26 1 CFIE27 Cancellation Finished Interrupt Enable 27 27 1 CFIE28 Cancellation Finished Interrupt Enable 28 28 1 CFIE29 Cancellation Finished Interrupt Enable 29 29 1 CFIE3 Cancellation Finished Interrupt Enable 3 3 1 CFIE30 Cancellation Finished Interrupt Enable 30 30 1 CFIE31 Cancellation Finished Interrupt Enable 31 31 1 CFIE4 Cancellation Finished Interrupt Enable 4 4 1 CFIE5 Cancellation Finished Interrupt Enable 5 5 1 CFIE6 Cancellation Finished Interrupt Enable 6 6 1 CFIE7 Cancellation Finished Interrupt Enable 7 7 1 CFIE8 Cancellation Finished Interrupt Enable 8 8 1 CFIE9 Cancellation Finished Interrupt Enable 9 9 1 TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write n 0x0 0x0 CR0 Cancellation Request 0 0 1 CR1 Cancellation Request 1 1 1 CR10 Cancellation Request 10 10 1 CR11 Cancellation Request 11 11 1 CR12 Cancellation Request 12 12 1 CR13 Cancellation Request 13 13 1 CR14 Cancellation Request 14 14 1 CR15 Cancellation Request 15 15 1 CR16 Cancellation Request 16 16 1 CR17 Cancellation Request 17 17 1 CR18 Cancellation Request 18 18 1 CR19 Cancellation Request 19 19 1 CR2 Cancellation Request 2 2 1 CR20 Cancellation Request 20 20 1 CR21 Cancellation Request 21 21 1 CR22 Cancellation Request 22 22 1 CR23 Cancellation Request 23 23 1 CR24 Cancellation Request 24 24 1 CR25 Cancellation Request 25 25 1 CR26 Cancellation Request 26 26 1 CR27 Cancellation Request 27 27 1 CR28 Cancellation Request 28 28 1 CR29 Cancellation Request 29 29 1 CR3 Cancellation Request 3 3 1 CR30 Cancellation Request 30 30 1 CR31 Cancellation Request 31 31 1 CR4 Cancellation Request 4 4 1 CR5 Cancellation Request 5 5 1 CR6 Cancellation Request 6 6 1 CR7 Cancellation Request 7 7 1 CR8 Cancellation Request 8 8 1 CR9 Cancellation Request 9 9 1 TXBRP Tx Buffer Request Pending 0xCC 32 read-only n 0x0 0x0 TRP0 Transmission Request Pending 0 0 1 read-only TRP1 Transmission Request Pending 1 1 1 read-only TRP10 Transmission Request Pending 10 10 1 read-only TRP11 Transmission Request Pending 11 11 1 read-only TRP12 Transmission Request Pending 12 12 1 read-only TRP13 Transmission Request Pending 13 13 1 read-only TRP14 Transmission Request Pending 14 14 1 read-only TRP15 Transmission Request Pending 15 15 1 read-only TRP16 Transmission Request Pending 16 16 1 read-only TRP17 Transmission Request Pending 17 17 1 read-only TRP18 Transmission Request Pending 18 18 1 read-only TRP19 Transmission Request Pending 19 19 1 read-only TRP2 Transmission Request Pending 2 2 1 read-only TRP20 Transmission Request Pending 20 20 1 read-only TRP21 Transmission Request Pending 21 21 1 read-only TRP22 Transmission Request Pending 22 22 1 read-only TRP23 Transmission Request Pending 23 23 1 read-only TRP24 Transmission Request Pending 24 24 1 read-only TRP25 Transmission Request Pending 25 25 1 read-only TRP26 Transmission Request Pending 26 26 1 read-only TRP27 Transmission Request Pending 27 27 1 read-only TRP28 Transmission Request Pending 28 28 1 read-only TRP29 Transmission Request Pending 29 29 1 read-only TRP3 Transmission Request Pending 3 3 1 read-only TRP30 Transmission Request Pending 30 30 1 read-only TRP31 Transmission Request Pending 31 31 1 read-only TRP4 Transmission Request Pending 4 4 1 read-only TRP5 Transmission Request Pending 5 5 1 read-only TRP6 Transmission Request Pending 6 6 1 read-only TRP7 Transmission Request Pending 7 7 1 read-only TRP8 Transmission Request Pending 8 8 1 read-only TRP9 Transmission Request Pending 9 9 1 read-only TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write n 0x0 0x0 TIE0 Transmission Interrupt Enable 0 0 1 TIE1 Transmission Interrupt Enable 1 1 1 TIE10 Transmission Interrupt Enable 10 10 1 TIE11 Transmission Interrupt Enable 11 11 1 TIE12 Transmission Interrupt Enable 12 12 1 TIE13 Transmission Interrupt Enable 13 13 1 TIE14 Transmission Interrupt Enable 14 14 1 TIE15 Transmission Interrupt Enable 15 15 1 TIE16 Transmission Interrupt Enable 16 16 1 TIE17 Transmission Interrupt Enable 17 17 1 TIE18 Transmission Interrupt Enable 18 18 1 TIE19 Transmission Interrupt Enable 19 19 1 TIE2 Transmission Interrupt Enable 2 2 1 TIE20 Transmission Interrupt Enable 20 20 1 TIE21 Transmission Interrupt Enable 21 21 1 TIE22 Transmission Interrupt Enable 22 22 1 TIE23 Transmission Interrupt Enable 23 23 1 TIE24 Transmission Interrupt Enable 24 24 1 TIE25 Transmission Interrupt Enable 25 25 1 TIE26 Transmission Interrupt Enable 26 26 1 TIE27 Transmission Interrupt Enable 27 27 1 TIE28 Transmission Interrupt Enable 28 28 1 TIE29 Transmission Interrupt Enable 29 29 1 TIE3 Transmission Interrupt Enable 3 3 1 TIE30 Transmission Interrupt Enable 30 30 1 TIE31 Transmission Interrupt Enable 31 31 1 TIE4 Transmission Interrupt Enable 4 4 1 TIE5 Transmission Interrupt Enable 5 5 1 TIE6 Transmission Interrupt Enable 6 6 1 TIE7 Transmission Interrupt Enable 7 7 1 TIE8 Transmission Interrupt Enable 8 8 1 TIE9 Transmission Interrupt Enable 9 9 1 TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only n 0x0 0x0 TO0 Transmission Occurred 0 0 1 read-only TO1 Transmission Occurred 1 1 1 read-only TO10 Transmission Occurred 10 10 1 read-only TO11 Transmission Occurred 11 11 1 read-only TO12 Transmission Occurred 12 12 1 read-only TO13 Transmission Occurred 13 13 1 read-only TO14 Transmission Occurred 14 14 1 read-only TO15 Transmission Occurred 15 15 1 read-only TO16 Transmission Occurred 16 16 1 read-only TO17 Transmission Occurred 17 17 1 read-only TO18 Transmission Occurred 18 18 1 read-only TO19 Transmission Occurred 19 19 1 read-only TO2 Transmission Occurred 2 2 1 read-only TO20 Transmission Occurred 20 20 1 read-only TO21 Transmission Occurred 21 21 1 read-only TO22 Transmission Occurred 22 22 1 read-only TO23 Transmission Occurred 23 23 1 read-only TO24 Transmission Occurred 24 24 1 read-only TO25 Transmission Occurred 25 25 1 read-only TO26 Transmission Occurred 26 26 1 read-only TO27 Transmission Occurred 27 27 1 read-only TO28 Transmission Occurred 28 28 1 read-only TO29 Transmission Occurred 29 29 1 read-only TO3 Transmission Occurred 3 3 1 read-only TO30 Transmission Occurred 30 30 1 read-only TO31 Transmission Occurred 31 31 1 read-only TO4 Transmission Occurred 4 4 1 read-only TO5 Transmission Occurred 5 5 1 read-only TO6 Transmission Occurred 6 6 1 read-only TO7 Transmission Occurred 7 7 1 read-only TO8 Transmission Occurred 8 8 1 read-only TO9 Transmission Occurred 9 9 1 read-only TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write n 0x0 0x0 EFAI Event FIFO Acknowledge Index 0 5 TXEFC Tx Event FIFO Configuration 0xF0 32 read-write n 0x0 0x0 EFS Event FIFO Size 16 6 EFSA Event FIFO Start Address 0 16 EFWM Event FIFO Watermark 24 6 TXEFS Tx Event FIFO Status 0xF4 32 read-only n 0x0 0x0 EFF Event FIFO Full 24 1 read-only EFFL Event FIFO Fill Level 0 6 read-only EFGI Event FIFO Get Index 8 5 read-only EFPI Event FIFO Put Index 16 5 read-only TEFL Tx Event FIFO Element Lost 25 1 read-only TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write n 0x0 0x0 TBDS Tx Buffer Data Field Size 0 3 TBDSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 TXFQS Tx FIFO / Queue Status 0xC4 32 read-only n 0x0 0x0 TFFL Tx FIFO Free Level 0 6 read-only TFGI Tx FIFO Get Index 8 5 read-only TFQF Tx FIFO/Queue Full 21 1 read-only TFQPI Tx FIFO/Queue Put Index 16 5 read-only XIDAM Extended ID AND Mask 0x90 32 read-write n 0x0 0x0 EIDM Extended ID Mask 0 29 XIDFC Extended ID Filter Configuration 0x88 32 read-write n 0x0 0x0 FLESA Filter List Extended Start Address 0 16 LSE List Size Extended 16 7 CAN1 Control Area Network CAN 0x0 0x0 0x200 registers n 0x0 0xFC registers n CAN1_INTREQ 16 CAN_CCCR CC Control 0x18 32 read-write n 0x0 0x0 ASM ASM Restricted Operation Mode 2 1 BRSE Bit Rate Switch Enable 9 1 CCE Configuration Change Enable 1 1 CSA Clock Stop Acknowledge 3 1 read-only CSR Clock Stop Request 4 1 DAR Disable Automatic Retransmission 6 1 EFBI Edge Filtering during Bus Integration 13 1 FDOE FD Operation Enable 8 1 INIT Initialization 0 1 MON Bus Monitoring Mode 5 1 NISO Non ISO Operation 15 1 PXHD Protocol Exception Handling Disable 12 1 TEST Test Mode Enable 7 1 TXP Transmit Pause 14 1 CAN_CREL Core Release 0x0 32 read-only n 0x0 0x0 REL Core Release 28 4 read-only STEP Step of Core Release 24 4 read-only SUBSTEP Sub-step of Core Release 20 4 read-only CAN_DBTP Fast Bit Timing and Prescaler 0xC 32 read-write n 0x0 0x0 DBRP Data Baud Rate Prescaler 16 5 DSJW Data (Re)Synchronization Jump Width 0 4 DTSEG1 Data time segment before sample point 8 5 DTSEG2 Data time segment after sample point 4 4 TDC Tranceiver Delay Compensation 23 1 CAN_ECR Error Counter 0x40 32 read-only n 0x0 0x0 CEL CAN Error Logging 16 8 read-only REC Receive Error Counter 8 7 read-only RP Receive Error Passive 15 1 read-only TEC Transmit Error Counter 0 8 read-only CAN_ENDN Endian 0x4 32 read-only n 0x0 0x0 ETV Endianness Test Value 0 32 read-only CAN_GFC Global Filter Configuration 0x80 32 read-write n 0x0 0x0 ANFE Accept Non-matching Frames Extended 2 2 ANFESelect RXF0 Accept in Rx FIFO 0 0x0 RXF1 Accept in Rx FIFO 1 0x1 REJECT Reject 0x2 ANFS Accept Non-matching Frames Standard 4 2 ANFSSelect RXF0 Accept in Rx FIFO 0 0x0 RXF1 Accept in Rx FIFO 1 0x1 REJECT Reject 0x2 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 CAN_HPMS High Priority Message Status 0x94 32 read-only n 0x0 0x0 BIDX Buffer Index 0 6 read-only FIDX Filter Index 8 7 read-only FLST Filter List 15 1 read-only MSI Message Storage Indicator 6 2 read-only MSISelect NONE No FIFO selected 0x0 LOST FIFO message lost 0x1 FIFO0 Message stored in FIFO 0 0x2 FIFO1 Message stored in FIFO 1 0x3 CAN_IE Interrupt Enable 0x54 32 read-write n 0x0 0x0 ARAE Access to Reserved Address Enable 29 1 BECE Bit Error Corrected Interrupt Enable 20 1 BEUE Bit Error Uncorrected Interrupt Enable 21 1 BOE Bus_Off Status Interrupt Enable 25 1 DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 1 ELOE Error Logging Overflow Interrupt Enable 22 1 EPE Error Passive Interrupt Enable 23 1 EWE Warning Status Interrupt Enable 24 1 HPME High Priority Message Interrupt Enable 8 1 MRAFE Message RAM Access Failure Interrupt Enable 17 1 PEAE Protocol Error in Arbitration Phase Enable 27 1 PEDE Protocol Error in Data Phase Enable 28 1 RF0FE Rx FIFO 0 Full Interrupt Enable 2 1 RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 1 RF0NE Rx FIFO 0 New Message Interrupt Enable 0 1 RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 RF1FE Rx FIFO 1 FIFO Full Interrupt Enable 6 1 RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 1 RF1NE Rx FIFO 1 New Message Interrupt Enable 4 1 RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 1 TCE Timestamp Completed Interrupt Enable 9 1 TCFE Transmission Cancellation Finished Interrupt Enable 10 1 TEFFE Tx Event FIFO Full Interrupt Enable 14 1 TEFLE Tx Event FIFO Element Lost Interrupt Enable 15 1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 TFEE Tx FIFO Empty Interrupt Enable 11 1 TOOE Timeout Occurred Interrupt Enable 18 1 TSWE Timestamp Wraparound Interrupt Enable 16 1 WDIE Watchdog Interrupt Interrupt Enable 26 1 CAN_ILE Interrupt Line Enable 0x5C 32 read-write n 0x0 0x0 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 CAN_ILS Interrupt Line Select 0x58 32 read-write n 0x0 0x0 ARAL Access to Reserved Address Line 29 1 BECL Bit Error Corrected Interrupt Line 20 1 BEUL Bit Error Uncorrected Interrupt Line 21 1 BOL Bus_Off Status Interrupt Line 25 1 DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 HPML High Priority Message Interrupt Line 8 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 PEAL Protocol Error in Arbitration Phase Line 27 1 PEDL Protocol Error in Data Phase Line 28 1 RF0FL Rx FIFO 0 Full Interrupt Line 2 1 RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 1 RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 RF1FL Rx FIFO 1 FIFO Full Interrupt Line 6 1 RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 1 RF1NL Rx FIFO 1 New Message Interrupt Line 4 1 RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TCL Timestamp Completed Interrupt Line 9 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Element Lost Interrupt Line 15 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TFEL Tx FIFO Empty Interrupt Line 11 1 TOOL Timeout Occurred Interrupt Line 18 1 TSWL Timestamp Wraparound Interrupt Line 16 1 WDIL Watchdog Interrupt Interrupt Line 26 1 CAN_IR Interrupt 0x50 32 read-write n 0x0 0x0 ARA Access to Reserved Address 29 1 BEC Bit Error Corrected 20 1 BEU Bit Error Uncorrected 21 1 BO Bus_Off Status 25 1 DRX Message stored to Dedicated Rx Buffer 19 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 HPM High Priority Message 8 1 MRAF Message RAM Access Failure 17 1 PEA Protocol Error in Arbitration Phase 27 1 PED Protocol Error in Data Phase 28 1 RF0F Rx FIFO 0 Full 2 1 RF0L Rx FIFO 0 Message Lost 3 1 RF0N Rx FIFO 0 New Message 0 1 RF0W Rx FIFO 0 Watermark Reached 1 1 RF1F Rx FIFO 1 FIFO Full 6 1 RF1L Rx FIFO 1 Message Lost 7 1 RF1N Rx FIFO 1 New Message 4 1 RF1W Rx FIFO 1 Watermark Reached 5 1 TC Timestamp Completed 9 1 TCF Transmission Cancellation Finished 10 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TFE Tx FIFO Empty 11 1 TOO Timeout Occurred 18 1 TSW Timestamp Wraparound 16 1 WDI Watchdog Interrupt 26 1 CAN_MRCFG Message RAM Configuration 0x8 32 read-write n 0x0 0x0 QOS Quality of Service 0 2 QOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 CAN_NBTP Nominal Bit Timing and Prescaler 0x1C 32 read-write n 0x0 0x0 NBRP Nominal Baud Rate Prescaler 16 9 NSJW Nominal (Re)Synchronization Jump Width 25 7 NTSEG1 Nominal Time segment before sample point 8 8 NTSEG2 Nominal Time segment after sample point 0 7 CAN_NDAT1 New Data 1 0x98 32 read-write n 0x0 0x0 ND0 New Data 0 0 1 ND1 New Data 1 1 1 ND10 New Data 10 10 1 ND11 New Data 11 11 1 ND12 New Data 12 12 1 ND13 New Data 13 13 1 ND14 New Data 14 14 1 ND15 New Data 15 15 1 ND16 New Data 16 16 1 ND17 New Data 17 17 1 ND18 New Data 18 18 1 ND19 New Data 19 19 1 ND2 New Data 2 2 1 ND20 New Data 20 20 1 ND21 New Data 21 21 1 ND22 New Data 22 22 1 ND23 New Data 23 23 1 ND24 New Data 24 24 1 ND25 New Data 25 25 1 ND26 New Data 26 26 1 ND27 New Data 27 27 1 ND28 New Data 28 28 1 ND29 New Data 29 29 1 ND3 New Data 3 3 1 ND30 New Data 30 30 1 ND31 New Data 31 31 1 ND4 New Data 4 4 1 ND5 New Data 5 5 1 ND6 New Data 6 6 1 ND7 New Data 7 7 1 ND8 New Data 8 8 1 ND9 New Data 9 9 1 CAN_NDAT2 New Data 2 0x9C 32 read-write n 0x0 0x0 ND32 New Data 32 0 1 ND33 New Data 33 1 1 ND34 New Data 34 2 1 ND35 New Data 35 3 1 ND36 New Data 36 4 1 ND37 New Data 37 5 1 ND38 New Data 38 6 1 ND39 New Data 39 7 1 ND40 New Data 40 8 1 ND41 New Data 41 9 1 ND42 New Data 42 10 1 ND43 New Data 43 11 1 ND44 New Data 44 12 1 ND45 New Data 45 13 1 ND46 New Data 46 14 1 ND47 New Data 47 15 1 ND48 New Data 48 16 1 ND49 New Data 49 17 1 ND50 New Data 50 18 1 ND51 New Data 51 19 1 ND52 New Data 52 20 1 ND53 New Data 53 21 1 ND54 New Data 54 22 1 ND55 New Data 55 23 1 ND56 New Data 56 24 1 ND57 New Data 57 25 1 ND58 New Data 58 26 1 ND59 New Data 59 27 1 ND60 New Data 60 28 1 ND61 New Data 61 29 1 ND62 New Data 62 30 1 ND63 New Data 63 31 1 CAN_PSR Protocol Status 0x44 32 read-only n 0x0 0x0 ACT Activity 3 2 read-only ACTSelect SYNC Node is synchronizing on CAN communication 0x0 IDLE Node is neither receiver nor transmitter 0x1 RX Node is operating as receiver 0x2 TX Node is operating as transmitter 0x3 BO Bus_Off Status 7 1 read-only DLEC Data Phase Last Error Code 8 3 read-only DLECSelect NONE No Error 0x0 STUFF Stuff Error 0x1 FORM Form Error 0x2 ACK Ack Error 0x3 BIT1 Bit1 Error 0x4 BIT0 Bit0 Error 0x5 CRC CRC Error 0x6 NC No Change 0x7 EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only LEC Last Error Code 0 3 read-only LECSelect NONE No Error 0x0 STUFF Stuff Error 0x1 FORM Form Error 0x2 ACK Ack Error 0x3 BIT1 Bit1 Error 0x4 BIT0 Bit0 Error 0x5 CRC CRC Error 0x6 NC No Change 0x7 PXE Protocol Exception Event 14 1 read-only RBRS BRS flag of last received CAN FD Message 12 1 read-only RESI ESI flag of last received CAN FD Message 11 1 read-only RFDF Received a CAN FD Message 13 1 read-only TDCV Transmitter Delay Compensation Value 16 7 read-only CAN_RWD RAM Watchdog 0x14 32 read-write n 0x0 0x0 WDC Watchdog Configuration 0 8 read-only WDV Watchdog Value 8 8 read-only CAN_RXBC Rx Buffer Configuration 0xAC 32 read-write n 0x0 0x0 RBSA Rx Buffer Start Address 0 16 CAN_RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write n 0x0 0x0 F0DS Rx FIFO 0 Data Field Size 0 3 F0DSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 F1DS Rx FIFO 1 Data Field Size 4 3 F1DSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 RBDS Rx Buffer Data Field Size 8 3 RBDSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 CAN_RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write n 0x0 0x0 F0AI Rx FIFO 0 Acknowledge Index 0 6 CAN_RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write n 0x0 0x0 F0OM FIFO 0 Operation Mode 31 1 F0S Rx FIFO 0 Size 16 7 F0SA Rx FIFO 0 Start Address 0 16 F0WM Rx FIFO 0 Watermark 24 7 CAN_RXF0S Rx FIFO 0 Status 0xA4 32 read-only n 0x0 0x0 F0F Rx FIFO 0 Full 24 1 read-only F0FL Rx FIFO 0 Fill Level 0 7 read-only F0GI Rx FIFO 0 Get Index 8 6 read-only F0PI Rx FIFO 0 Put Index 16 6 read-only RF0L Rx FIFO 0 Message Lost 25 1 read-only CAN_RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write n 0x0 0x0 F1AI Rx FIFO 1 Acknowledge Index 0 6 CAN_RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write n 0x0 0x0 F1OM FIFO 1 Operation Mode 31 1 F1S Rx FIFO 1 Size 16 7 F1SA Rx FIFO 1 Start Address 0 16 F1WM Rx FIFO 1 Watermark 24 7 CAN_RXF1S Rx FIFO 1 Status 0xB4 32 read-only n 0x0 0x0 DMS Debug Message Status 30 2 read-only DMSSelect IDLE Idle state 0x0 DBGA Debug message A received 0x1 DBGB Debug message A/B received 0x2 DBGC Debug message A/B/C received, DMA request set 0x3 F1F Rx FIFO 1 Full 24 1 read-only F1FL Rx FIFO 1 Fill Level 0 7 read-only F1GI Rx FIFO 1 Get Index 8 6 read-only F1PI Rx FIFO 1 Put Index 16 6 read-only RF1L Rx FIFO 1 Message Lost 25 1 read-only CAN_SIDFC Standard ID Filter Configuration 0x84 32 read-write n 0x0 0x0 FLSSA Filter List Standard Start Address 0 16 LSS List Size Standard 16 8 CAN_TDCR Extended ID Filter Configuration 0x48 32 read-write n 0x0 0x0 TDCF Transmitter Delay Compensation Filter Length 0 7 read-only TDCO Transmitter Delay Compensation Offset 8 7 CAN_TEST Test 0x10 32 read-write n 0x0 0x0 LBCK Loop Back Mode 4 1 RX Receive Pin 7 1 read-only TX Control of Transmit Pin 5 2 TXSelect CORE TX controlled by CAN core 0x0 SAMPLE TX monitoring sample point 0x1 DOMINANT Dominant (0) level at pin CAN_TX 0x2 RECESSIVE Recessive (1) level at pin CAN_TX 0x3 CAN_TOCC Timeout Counter Configuration 0x28 32 read-write n 0x0 0x0 ETOC Enable Timeout Counter 0 1 TOP Timeout Period 16 16 TOS Timeout Select 1 2 TOSSelect CONT Continuout operation 0x0 TXEF Timeout controlled by TX Event FIFO 0x1 RXF0 Timeout controlled by Rx FIFO 0 0x2 RXF1 Timeout controlled by Rx FIFO 1 0x3 CAN_TOCV Timeout Counter Value 0x2C 32 read-write n 0x0 0x0 TOC Timeout Counter 0 16 CAN_TSCC Timestamp Counter Configuration 0x20 32 read-write n 0x0 0x0 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSSSelect ZERO Timestamp counter value always 0x0000 0x0 INC Timestamp counter value incremented by TCP 0x1 EXT External timestamp counter value used 0x2 CAN_TSCV Timestamp Counter Value 0x24 32 read-only n 0x0 0x0 TSC Timestamp Counter 0 16 read-only CAN_TXBAR Tx Buffer Add Request 0xD0 32 read-write n 0x0 0x0 AR0 Add Request 0 0 1 AR1 Add Request 1 1 1 AR10 Add Request 10 10 1 AR11 Add Request 11 11 1 AR12 Add Request 12 12 1 AR13 Add Request 13 13 1 AR14 Add Request 14 14 1 AR15 Add Request 15 15 1 AR16 Add Request 16 16 1 AR17 Add Request 17 17 1 AR18 Add Request 18 18 1 AR19 Add Request 19 19 1 AR2 Add Request 2 2 1 AR20 Add Request 20 20 1 AR21 Add Request 21 21 1 AR22 Add Request 22 22 1 AR23 Add Request 23 23 1 AR24 Add Request 24 24 1 AR25 Add Request 25 25 1 AR26 Add Request 26 26 1 AR27 Add Request 27 27 1 AR28 Add Request 28 28 1 AR29 Add Request 29 29 1 AR3 Add Request 3 3 1 AR30 Add Request 30 30 1 AR31 Add Request 31 31 1 AR4 Add Request 4 4 1 AR5 Add Request 5 5 1 AR6 Add Request 6 6 1 AR7 Add Request 7 7 1 AR8 Add Request 8 8 1 AR9 Add Request 9 9 1 CAN_TXBC Tx Buffer Configuration 0xC0 32 read-write n 0x0 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 TBSA Tx Buffers Start Address 0 16 TFQM Tx FIFO/Queue Mode 30 1 TFQS Transmit FIFO/Queue Size 24 6 CAN_TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only n 0x0 0x0 CF0 Tx Buffer Cancellation Finished 0 0 1 read-only CF1 Tx Buffer Cancellation Finished 1 1 1 read-only CF10 Tx Buffer Cancellation Finished 10 10 1 read-only CF11 Tx Buffer Cancellation Finished 11 11 1 read-only CF12 Tx Buffer Cancellation Finished 12 12 1 read-only CF13 Tx Buffer Cancellation Finished 13 13 1 read-only CF14 Tx Buffer Cancellation Finished 14 14 1 read-only CF15 Tx Buffer Cancellation Finished 15 15 1 read-only CF16 Tx Buffer Cancellation Finished 16 16 1 read-only CF17 Tx Buffer Cancellation Finished 17 17 1 read-only CF18 Tx Buffer Cancellation Finished 18 18 1 read-only CF19 Tx Buffer Cancellation Finished 19 19 1 read-only CF2 Tx Buffer Cancellation Finished 2 2 1 read-only CF20 Tx Buffer Cancellation Finished 20 20 1 read-only CF21 Tx Buffer Cancellation Finished 21 21 1 read-only CF22 Tx Buffer Cancellation Finished 22 22 1 read-only CF23 Tx Buffer Cancellation Finished 23 23 1 read-only CF24 Tx Buffer Cancellation Finished 24 24 1 read-only CF25 Tx Buffer Cancellation Finished 25 25 1 read-only CF26 Tx Buffer Cancellation Finished 26 26 1 read-only CF27 Tx Buffer Cancellation Finished 27 27 1 read-only CF28 Tx Buffer Cancellation Finished 28 28 1 read-only CF29 Tx Buffer Cancellation Finished 29 29 1 read-only CF3 Tx Buffer Cancellation Finished 3 3 1 read-only CF30 Tx Buffer Cancellation Finished 30 30 1 read-only CF31 Tx Buffer Cancellation Finished 31 31 1 read-only CF4 Tx Buffer Cancellation Finished 4 4 1 read-only CF5 Tx Buffer Cancellation Finished 5 5 1 read-only CF6 Tx Buffer Cancellation Finished 6 6 1 read-only CF7 Tx Buffer Cancellation Finished 7 7 1 read-only CF8 Tx Buffer Cancellation Finished 8 8 1 read-only CF9 Tx Buffer Cancellation Finished 9 9 1 read-only CAN_TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write n 0x0 0x0 CFIE0 Cancellation Finished Interrupt Enable 0 0 1 CFIE1 Cancellation Finished Interrupt Enable 1 1 1 CFIE10 Cancellation Finished Interrupt Enable 10 10 1 CFIE11 Cancellation Finished Interrupt Enable 11 11 1 CFIE12 Cancellation Finished Interrupt Enable 12 12 1 CFIE13 Cancellation Finished Interrupt Enable 13 13 1 CFIE14 Cancellation Finished Interrupt Enable 14 14 1 CFIE15 Cancellation Finished Interrupt Enable 15 15 1 CFIE16 Cancellation Finished Interrupt Enable 16 16 1 CFIE17 Cancellation Finished Interrupt Enable 17 17 1 CFIE18 Cancellation Finished Interrupt Enable 18 18 1 CFIE19 Cancellation Finished Interrupt Enable 19 19 1 CFIE2 Cancellation Finished Interrupt Enable 2 2 1 CFIE20 Cancellation Finished Interrupt Enable 20 20 1 CFIE21 Cancellation Finished Interrupt Enable 21 21 1 CFIE22 Cancellation Finished Interrupt Enable 22 22 1 CFIE23 Cancellation Finished Interrupt Enable 23 23 1 CFIE24 Cancellation Finished Interrupt Enable 24 24 1 CFIE25 Cancellation Finished Interrupt Enable 25 25 1 CFIE26 Cancellation Finished Interrupt Enable 26 26 1 CFIE27 Cancellation Finished Interrupt Enable 27 27 1 CFIE28 Cancellation Finished Interrupt Enable 28 28 1 CFIE29 Cancellation Finished Interrupt Enable 29 29 1 CFIE3 Cancellation Finished Interrupt Enable 3 3 1 CFIE30 Cancellation Finished Interrupt Enable 30 30 1 CFIE31 Cancellation Finished Interrupt Enable 31 31 1 CFIE4 Cancellation Finished Interrupt Enable 4 4 1 CFIE5 Cancellation Finished Interrupt Enable 5 5 1 CFIE6 Cancellation Finished Interrupt Enable 6 6 1 CFIE7 Cancellation Finished Interrupt Enable 7 7 1 CFIE8 Cancellation Finished Interrupt Enable 8 8 1 CFIE9 Cancellation Finished Interrupt Enable 9 9 1 CAN_TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write n 0x0 0x0 CR0 Cancellation Request 0 0 1 CR1 Cancellation Request 1 1 1 CR10 Cancellation Request 10 10 1 CR11 Cancellation Request 11 11 1 CR12 Cancellation Request 12 12 1 CR13 Cancellation Request 13 13 1 CR14 Cancellation Request 14 14 1 CR15 Cancellation Request 15 15 1 CR16 Cancellation Request 16 16 1 CR17 Cancellation Request 17 17 1 CR18 Cancellation Request 18 18 1 CR19 Cancellation Request 19 19 1 CR2 Cancellation Request 2 2 1 CR20 Cancellation Request 20 20 1 CR21 Cancellation Request 21 21 1 CR22 Cancellation Request 22 22 1 CR23 Cancellation Request 23 23 1 CR24 Cancellation Request 24 24 1 CR25 Cancellation Request 25 25 1 CR26 Cancellation Request 26 26 1 CR27 Cancellation Request 27 27 1 CR28 Cancellation Request 28 28 1 CR29 Cancellation Request 29 29 1 CR3 Cancellation Request 3 3 1 CR30 Cancellation Request 30 30 1 CR31 Cancellation Request 31 31 1 CR4 Cancellation Request 4 4 1 CR5 Cancellation Request 5 5 1 CR6 Cancellation Request 6 6 1 CR7 Cancellation Request 7 7 1 CR8 Cancellation Request 8 8 1 CR9 Cancellation Request 9 9 1 CAN_TXBRP Tx Buffer Request Pending 0xCC 32 read-only n 0x0 0x0 TRP0 Transmission Request Pending 0 0 1 read-only TRP1 Transmission Request Pending 1 1 1 read-only TRP10 Transmission Request Pending 10 10 1 read-only TRP11 Transmission Request Pending 11 11 1 read-only TRP12 Transmission Request Pending 12 12 1 read-only TRP13 Transmission Request Pending 13 13 1 read-only TRP14 Transmission Request Pending 14 14 1 read-only TRP15 Transmission Request Pending 15 15 1 read-only TRP16 Transmission Request Pending 16 16 1 read-only TRP17 Transmission Request Pending 17 17 1 read-only TRP18 Transmission Request Pending 18 18 1 read-only TRP19 Transmission Request Pending 19 19 1 read-only TRP2 Transmission Request Pending 2 2 1 read-only TRP20 Transmission Request Pending 20 20 1 read-only TRP21 Transmission Request Pending 21 21 1 read-only TRP22 Transmission Request Pending 22 22 1 read-only TRP23 Transmission Request Pending 23 23 1 read-only TRP24 Transmission Request Pending 24 24 1 read-only TRP25 Transmission Request Pending 25 25 1 read-only TRP26 Transmission Request Pending 26 26 1 read-only TRP27 Transmission Request Pending 27 27 1 read-only TRP28 Transmission Request Pending 28 28 1 read-only TRP29 Transmission Request Pending 29 29 1 read-only TRP3 Transmission Request Pending 3 3 1 read-only TRP30 Transmission Request Pending 30 30 1 read-only TRP31 Transmission Request Pending 31 31 1 read-only TRP4 Transmission Request Pending 4 4 1 read-only TRP5 Transmission Request Pending 5 5 1 read-only TRP6 Transmission Request Pending 6 6 1 read-only TRP7 Transmission Request Pending 7 7 1 read-only TRP8 Transmission Request Pending 8 8 1 read-only TRP9 Transmission Request Pending 9 9 1 read-only CAN_TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write n 0x0 0x0 TIE0 Transmission Interrupt Enable 0 0 1 TIE1 Transmission Interrupt Enable 1 1 1 TIE10 Transmission Interrupt Enable 10 10 1 TIE11 Transmission Interrupt Enable 11 11 1 TIE12 Transmission Interrupt Enable 12 12 1 TIE13 Transmission Interrupt Enable 13 13 1 TIE14 Transmission Interrupt Enable 14 14 1 TIE15 Transmission Interrupt Enable 15 15 1 TIE16 Transmission Interrupt Enable 16 16 1 TIE17 Transmission Interrupt Enable 17 17 1 TIE18 Transmission Interrupt Enable 18 18 1 TIE19 Transmission Interrupt Enable 19 19 1 TIE2 Transmission Interrupt Enable 2 2 1 TIE20 Transmission Interrupt Enable 20 20 1 TIE21 Transmission Interrupt Enable 21 21 1 TIE22 Transmission Interrupt Enable 22 22 1 TIE23 Transmission Interrupt Enable 23 23 1 TIE24 Transmission Interrupt Enable 24 24 1 TIE25 Transmission Interrupt Enable 25 25 1 TIE26 Transmission Interrupt Enable 26 26 1 TIE27 Transmission Interrupt Enable 27 27 1 TIE28 Transmission Interrupt Enable 28 28 1 TIE29 Transmission Interrupt Enable 29 29 1 TIE3 Transmission Interrupt Enable 3 3 1 TIE30 Transmission Interrupt Enable 30 30 1 TIE31 Transmission Interrupt Enable 31 31 1 TIE4 Transmission Interrupt Enable 4 4 1 TIE5 Transmission Interrupt Enable 5 5 1 TIE6 Transmission Interrupt Enable 6 6 1 TIE7 Transmission Interrupt Enable 7 7 1 TIE8 Transmission Interrupt Enable 8 8 1 TIE9 Transmission Interrupt Enable 9 9 1 CAN_TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only n 0x0 0x0 TO0 Transmission Occurred 0 0 1 read-only TO1 Transmission Occurred 1 1 1 read-only TO10 Transmission Occurred 10 10 1 read-only TO11 Transmission Occurred 11 11 1 read-only TO12 Transmission Occurred 12 12 1 read-only TO13 Transmission Occurred 13 13 1 read-only TO14 Transmission Occurred 14 14 1 read-only TO15 Transmission Occurred 15 15 1 read-only TO16 Transmission Occurred 16 16 1 read-only TO17 Transmission Occurred 17 17 1 read-only TO18 Transmission Occurred 18 18 1 read-only TO19 Transmission Occurred 19 19 1 read-only TO2 Transmission Occurred 2 2 1 read-only TO20 Transmission Occurred 20 20 1 read-only TO21 Transmission Occurred 21 21 1 read-only TO22 Transmission Occurred 22 22 1 read-only TO23 Transmission Occurred 23 23 1 read-only TO24 Transmission Occurred 24 24 1 read-only TO25 Transmission Occurred 25 25 1 read-only TO26 Transmission Occurred 26 26 1 read-only TO27 Transmission Occurred 27 27 1 read-only TO28 Transmission Occurred 28 28 1 read-only TO29 Transmission Occurred 29 29 1 read-only TO3 Transmission Occurred 3 3 1 read-only TO30 Transmission Occurred 30 30 1 read-only TO31 Transmission Occurred 31 31 1 read-only TO4 Transmission Occurred 4 4 1 read-only TO5 Transmission Occurred 5 5 1 read-only TO6 Transmission Occurred 6 6 1 read-only TO7 Transmission Occurred 7 7 1 read-only TO8 Transmission Occurred 8 8 1 read-only TO9 Transmission Occurred 9 9 1 read-only CAN_TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write n 0x0 0x0 EFAI Event FIFO Acknowledge Index 0 5 CAN_TXEFC Tx Event FIFO Configuration 0xF0 32 read-write n 0x0 0x0 EFS Event FIFO Size 16 6 EFSA Event FIFO Start Address 0 16 EFWM Event FIFO Watermark 24 6 CAN_TXEFS Tx Event FIFO Status 0xF4 32 read-only n 0x0 0x0 EFF Event FIFO Full 24 1 read-only EFFL Event FIFO Fill Level 0 6 read-only EFGI Event FIFO Get Index 8 5 read-only EFPI Event FIFO Put Index 16 5 read-only TEFL Tx Event FIFO Element Lost 25 1 read-only CAN_TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write n 0x0 0x0 TBDS Tx Buffer Data Field Size 0 3 TBDSSelect DATA8 8 byte data field 0x0 DATA12 12 byte data field 0x1 DATA16 16 byte data field 0x2 DATA20 20 byte data field 0x3 DATA24 24 byte data field 0x4 DATA32 32 byte data field 0x5 DATA48 48 byte data field 0x6 DATA64 64 byte data field 0x7 CAN_TXFQS Tx FIFO / Queue Status 0xC4 32 read-only n 0x0 0x0 TFFL Tx FIFO Free Level 0 6 read-only TFGI Tx FIFO Get Index 8 5 read-only TFQF Tx FIFO/Queue Full 21 1 read-only TFQPI Tx FIFO/Queue Put Index 16 5 read-only CAN_XIDAM Extended ID AND Mask 0x90 32 read-write n 0x0 0x0 EIDM Extended ID Mask 0 29 CAN_XIDFC Extended ID Filter Configuration 0x88 32 read-write n 0x0 0x0 FLESA Filter List Extended Start Address 0 16 LSE List Size Extended 16 7 CCCR CC Control 0x18 32 read-write n 0x0 0x0 ASM ASM Restricted Operation Mode 2 1 BRSE Bit Rate Switch Enable 9 1 CCE Configuration Change Enable 1 1 CSA Clock Stop Acknowledge 3 1 read-only CSR Clock Stop Request 4 1 DAR Disable Automatic Retransmission 6 1 EFBI Edge Filtering during Bus Integration 13 1 FDOE FD Operation Enable 8 1 INIT Initialization 0 1 MON Bus Monitoring Mode 5 1 NISO Non ISO Operation 15 1 PXHD Protocol Exception Handling Disable 12 1 TEST Test Mode Enable 7 1 TXP Transmit Pause 14 1 CREL Core Release 0x0 32 read-only n 0x0 0x0 REL Core Release 28 4 read-only STEP Step of Core Release 24 4 read-only SUBSTEP Sub-step of Core Release 20 4 read-only DBTP Fast Bit Timing and Prescaler 0xC 32 read-write n 0x0 0x0 DBRP Data Baud Rate Prescaler 16 5 DSJW Data (Re)Synchronization Jump Width 0 4 DTSEG1 Data time segment before sample point 8 5 DTSEG2 Data time segment after sample point 4 4 TDC Tranceiver Delay Compensation 23 1 ECR Error Counter 0x40 32 read-only n 0x0 0x0 CEL CAN Error Logging 16 8 read-only REC Receive Error Counter 8 7 read-only RP Receive Error Passive 15 1 read-only TEC Transmit Error Counter 0 8 read-only ENDN Endian 0x4 32 read-only n 0x0 0x0 ETV Endianness Test Value 0 32 read-only GFC Global Filter Configuration 0x80 32 read-write n 0x0 0x0 ANFE Accept Non-matching Frames Extended 2 2 ANFESelect RXF0 Accept in Rx FIFO 0 0 RXF1 Accept in Rx FIFO 1 1 REJECT Reject 2 ANFS Accept Non-matching Frames Standard 4 2 ANFSSelect RXF0 Accept in Rx FIFO 0 0 RXF1 Accept in Rx FIFO 1 1 REJECT Reject 2 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 HPMS High Priority Message Status 0x94 32 read-only n 0x0 0x0 BIDX Buffer Index 0 6 read-only FIDX Filter Index 8 7 read-only FLST Filter List 15 1 read-only MSI Message Storage Indicator 6 2 read-only MSISelect NONE No FIFO selected 0 LOST FIFO message lost 1 FIFO0 Message stored in FIFO 0 2 FIFO1 Message stored in FIFO 1 3 IE Interrupt Enable 0x54 32 read-write n 0x0 0x0 ARAE Access to Reserved Address Enable 29 1 BECE Bit Error Corrected Interrupt Enable 20 1 BEUE Bit Error Uncorrected Interrupt Enable 21 1 BOE Bus_Off Status Interrupt Enable 25 1 DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 1 ELOE Error Logging Overflow Interrupt Enable 22 1 EPE Error Passive Interrupt Enable 23 1 EWE Warning Status Interrupt Enable 24 1 HPME High Priority Message Interrupt Enable 8 1 MRAFE Message RAM Access Failure Interrupt Enable 17 1 PEAE Protocol Error in Arbitration Phase Enable 27 1 PEDE Protocol Error in Data Phase Enable 28 1 RF0FE Rx FIFO 0 Full Interrupt Enable 2 1 RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 1 RF0NE Rx FIFO 0 New Message Interrupt Enable 0 1 RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 RF1FE Rx FIFO 1 FIFO Full Interrupt Enable 6 1 RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 1 RF1NE Rx FIFO 1 New Message Interrupt Enable 4 1 RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 1 TCE Timestamp Completed Interrupt Enable 9 1 TCFE Transmission Cancellation Finished Interrupt Enable 10 1 TEFFE Tx Event FIFO Full Interrupt Enable 14 1 TEFLE Tx Event FIFO Element Lost Interrupt Enable 15 1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 TFEE Tx FIFO Empty Interrupt Enable 11 1 TOOE Timeout Occurred Interrupt Enable 18 1 TSWE Timestamp Wraparound Interrupt Enable 16 1 WDIE Watchdog Interrupt Interrupt Enable 26 1 ILE Interrupt Line Enable 0x5C 32 read-write n 0x0 0x0 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 ILS Interrupt Line Select 0x58 32 read-write n 0x0 0x0 ARAL Access to Reserved Address Line 29 1 BECL Bit Error Corrected Interrupt Line 20 1 BEUL Bit Error Uncorrected Interrupt Line 21 1 BOL Bus_Off Status Interrupt Line 25 1 DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 HPML High Priority Message Interrupt Line 8 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 PEAL Protocol Error in Arbitration Phase Line 27 1 PEDL Protocol Error in Data Phase Line 28 1 RF0FL Rx FIFO 0 Full Interrupt Line 2 1 RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 1 RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 RF1FL Rx FIFO 1 FIFO Full Interrupt Line 6 1 RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 1 RF1NL Rx FIFO 1 New Message Interrupt Line 4 1 RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TCL Timestamp Completed Interrupt Line 9 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Element Lost Interrupt Line 15 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TFEL Tx FIFO Empty Interrupt Line 11 1 TOOL Timeout Occurred Interrupt Line 18 1 TSWL Timestamp Wraparound Interrupt Line 16 1 WDIL Watchdog Interrupt Interrupt Line 26 1 IR Interrupt 0x50 32 read-write n 0x0 0x0 ARA Access to Reserved Address 29 1 BEC Bit Error Corrected 20 1 BEU Bit Error Uncorrected 21 1 BO Bus_Off Status 25 1 DRX Message stored to Dedicated Rx Buffer 19 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 HPM High Priority Message 8 1 MRAF Message RAM Access Failure 17 1 PEA Protocol Error in Arbitration Phase 27 1 PED Protocol Error in Data Phase 28 1 RF0F Rx FIFO 0 Full 2 1 RF0L Rx FIFO 0 Message Lost 3 1 RF0N Rx FIFO 0 New Message 0 1 RF0W Rx FIFO 0 Watermark Reached 1 1 RF1F Rx FIFO 1 FIFO Full 6 1 RF1L Rx FIFO 1 Message Lost 7 1 RF1N Rx FIFO 1 New Message 4 1 RF1W Rx FIFO 1 Watermark Reached 5 1 TC Timestamp Completed 9 1 TCF Transmission Cancellation Finished 10 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TFE Tx FIFO Empty 11 1 TOO Timeout Occurred 18 1 TSW Timestamp Wraparound 16 1 WDI Watchdog Interrupt 26 1 MRCFG Message RAM Configuration 0x8 32 read-write n 0x0 0x0 QOS Quality of Service 0 2 QOSSelect DISABLE Background (no sensitive operation) 0 LOW Sensitive Bandwidth 1 MEDIUM Sensitive Latency 2 HIGH Critical Latency 3 NBTP Nominal Bit Timing and Prescaler 0x1C 32 read-write n 0x0 0x0 NBRP Nominal Baud Rate Prescaler 16 9 NSJW Nominal (Re)Synchronization Jump Width 25 7 NTSEG1 Nominal Time segment before sample point 8 8 NTSEG2 Nominal Time segment after sample point 0 7 NDAT1 New Data 1 0x98 32 read-write n 0x0 0x0 ND0 New Data 0 0 1 ND1 New Data 1 1 1 ND10 New Data 10 10 1 ND11 New Data 11 11 1 ND12 New Data 12 12 1 ND13 New Data 13 13 1 ND14 New Data 14 14 1 ND15 New Data 15 15 1 ND16 New Data 16 16 1 ND17 New Data 17 17 1 ND18 New Data 18 18 1 ND19 New Data 19 19 1 ND2 New Data 2 2 1 ND20 New Data 20 20 1 ND21 New Data 21 21 1 ND22 New Data 22 22 1 ND23 New Data 23 23 1 ND24 New Data 24 24 1 ND25 New Data 25 25 1 ND26 New Data 26 26 1 ND27 New Data 27 27 1 ND28 New Data 28 28 1 ND29 New Data 29 29 1 ND3 New Data 3 3 1 ND30 New Data 30 30 1 ND31 New Data 31 31 1 ND4 New Data 4 4 1 ND5 New Data 5 5 1 ND6 New Data 6 6 1 ND7 New Data 7 7 1 ND8 New Data 8 8 1 ND9 New Data 9 9 1 NDAT2 New Data 2 0x9C 32 read-write n 0x0 0x0 ND32 New Data 32 0 1 ND33 New Data 33 1 1 ND34 New Data 34 2 1 ND35 New Data 35 3 1 ND36 New Data 36 4 1 ND37 New Data 37 5 1 ND38 New Data 38 6 1 ND39 New Data 39 7 1 ND40 New Data 40 8 1 ND41 New Data 41 9 1 ND42 New Data 42 10 1 ND43 New Data 43 11 1 ND44 New Data 44 12 1 ND45 New Data 45 13 1 ND46 New Data 46 14 1 ND47 New Data 47 15 1 ND48 New Data 48 16 1 ND49 New Data 49 17 1 ND50 New Data 50 18 1 ND51 New Data 51 19 1 ND52 New Data 52 20 1 ND53 New Data 53 21 1 ND54 New Data 54 22 1 ND55 New Data 55 23 1 ND56 New Data 56 24 1 ND57 New Data 57 25 1 ND58 New Data 58 26 1 ND59 New Data 59 27 1 ND60 New Data 60 28 1 ND61 New Data 61 29 1 ND62 New Data 62 30 1 ND63 New Data 63 31 1 PSR Protocol Status 0x44 32 read-only n 0x0 0x0 ACT Activity 3 2 read-only ACTSelect SYNC Node is synchronizing on CAN communication 0 IDLE Node is neither receiver nor transmitter 1 RX Node is operating as receiver 2 TX Node is operating as transmitter 3 BO Bus_Off Status 7 1 read-only DLEC Data Phase Last Error Code 8 3 read-only DLECSelect NONE No Error 0 STUFF Stuff Error 1 FORM Form Error 2 ACK Ack Error 3 BIT1 Bit1 Error 4 BIT0 Bit0 Error 5 CRC CRC Error 6 NC No Change 7 EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only LEC Last Error Code 0 3 read-only LECSelect NONE No Error 0 STUFF Stuff Error 1 FORM Form Error 2 ACK Ack Error 3 BIT1 Bit1 Error 4 BIT0 Bit0 Error 5 CRC CRC Error 6 NC No Change 7 PXE Protocol Exception Event 14 1 read-only RBRS BRS flag of last received CAN FD Message 12 1 read-only RESI ESI flag of last received CAN FD Message 11 1 read-only RFDF Received a CAN FD Message 13 1 read-only TDCV Transmitter Delay Compensation Value 16 7 read-only RWD RAM Watchdog 0x14 32 read-write n 0x0 0x0 WDC Watchdog Configuration 0 8 read-only WDV Watchdog Value 8 8 read-only RXBC Rx Buffer Configuration 0xAC 32 read-write n 0x0 0x0 RBSA Rx Buffer Start Address 0 16 RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 read-write n 0x0 0x0 F0DS Rx FIFO 0 Data Field Size 0 3 F0DSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 F1DS Rx FIFO 1 Data Field Size 4 3 F1DSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 RBDS Rx Buffer Data Field Size 8 3 RBDSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 RXF0A Rx FIFO 0 Acknowledge 0xA8 32 read-write n 0x0 0x0 F0AI Rx FIFO 0 Acknowledge Index 0 6 RXF0C Rx FIFO 0 Configuration 0xA0 32 read-write n 0x0 0x0 F0OM FIFO 0 Operation Mode 31 1 F0S Rx FIFO 0 Size 16 7 F0SA Rx FIFO 0 Start Address 0 16 F0WM Rx FIFO 0 Watermark 24 7 RXF0S Rx FIFO 0 Status 0xA4 32 read-only n 0x0 0x0 F0F Rx FIFO 0 Full 24 1 read-only F0FL Rx FIFO 0 Fill Level 0 7 read-only F0GI Rx FIFO 0 Get Index 8 6 read-only F0PI Rx FIFO 0 Put Index 16 6 read-only RF0L Rx FIFO 0 Message Lost 25 1 read-only RXF1A Rx FIFO 1 Acknowledge 0xB8 32 read-write n 0x0 0x0 F1AI Rx FIFO 1 Acknowledge Index 0 6 RXF1C Rx FIFO 1 Configuration 0xB0 32 read-write n 0x0 0x0 F1OM FIFO 1 Operation Mode 31 1 F1S Rx FIFO 1 Size 16 7 F1SA Rx FIFO 1 Start Address 0 16 F1WM Rx FIFO 1 Watermark 24 7 RXF1S Rx FIFO 1 Status 0xB4 32 read-only n 0x0 0x0 DMS Debug Message Status 30 2 read-only DMSSelect IDLE Idle state 0 DBGA Debug message A received 1 DBGB Debug message A/B received 2 DBGC Debug message A/B/C received, DMA request set 3 F1F Rx FIFO 1 Full 24 1 read-only F1FL Rx FIFO 1 Fill Level 0 7 read-only F1GI Rx FIFO 1 Get Index 8 6 read-only F1PI Rx FIFO 1 Put Index 16 6 read-only RF1L Rx FIFO 1 Message Lost 25 1 read-only SIDFC Standard ID Filter Configuration 0x84 32 read-write n 0x0 0x0 FLSSA Filter List Standard Start Address 0 16 LSS List Size Standard 16 8 TDCR Extended ID Filter Configuration 0x48 32 read-write n 0x0 0x0 TDCF Transmitter Delay Compensation Filter Length 0 7 read-only TDCO Transmitter Delay Compensation Offset 8 7 TEST Test 0x10 32 read-write n 0x0 0x0 LBCK Loop Back Mode 4 1 RX Receive Pin 7 1 read-only TX Control of Transmit Pin 5 2 TXSelect CORE TX controlled by CAN core 0 SAMPLE TX monitoring sample point 1 DOMINANT Dominant (0) level at pin CAN_TX 2 RECESSIVE Recessive (1) level at pin CAN_TX 3 TOCC Timeout Counter Configuration 0x28 32 read-write n 0x0 0x0 ETOC Enable Timeout Counter 0 1 TOP Timeout Period 16 16 TOS Timeout Select 1 2 TOSSelect CONT Continuout operation 0 TXEF Timeout controlled by TX Event FIFO 1 RXF0 Timeout controlled by Rx FIFO 0 2 RXF1 Timeout controlled by Rx FIFO 1 3 TOCV Timeout Counter Value 0x2C 32 read-write n 0x0 0x0 TOC Timeout Counter 0 16 TSCC Timestamp Counter Configuration 0x20 32 read-write n 0x0 0x0 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSSSelect ZERO Timestamp counter value always 0x0000 0 INC Timestamp counter value incremented by TCP 1 EXT External timestamp counter value used 2 TSCV Timestamp Counter Value 0x24 32 read-only n 0x0 0x0 TSC Timestamp Counter 0 16 read-only TXBAR Tx Buffer Add Request 0xD0 32 read-write n 0x0 0x0 AR0 Add Request 0 0 1 AR1 Add Request 1 1 1 AR10 Add Request 10 10 1 AR11 Add Request 11 11 1 AR12 Add Request 12 12 1 AR13 Add Request 13 13 1 AR14 Add Request 14 14 1 AR15 Add Request 15 15 1 AR16 Add Request 16 16 1 AR17 Add Request 17 17 1 AR18 Add Request 18 18 1 AR19 Add Request 19 19 1 AR2 Add Request 2 2 1 AR20 Add Request 20 20 1 AR21 Add Request 21 21 1 AR22 Add Request 22 22 1 AR23 Add Request 23 23 1 AR24 Add Request 24 24 1 AR25 Add Request 25 25 1 AR26 Add Request 26 26 1 AR27 Add Request 27 27 1 AR28 Add Request 28 28 1 AR29 Add Request 29 29 1 AR3 Add Request 3 3 1 AR30 Add Request 30 30 1 AR31 Add Request 31 31 1 AR4 Add Request 4 4 1 AR5 Add Request 5 5 1 AR6 Add Request 6 6 1 AR7 Add Request 7 7 1 AR8 Add Request 8 8 1 AR9 Add Request 9 9 1 TXBC Tx Buffer Configuration 0xC0 32 read-write n 0x0 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 TBSA Tx Buffers Start Address 0 16 TFQM Tx FIFO/Queue Mode 30 1 TFQS Transmit FIFO/Queue Size 24 6 TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only n 0x0 0x0 CF0 Tx Buffer Cancellation Finished 0 0 1 read-only CF1 Tx Buffer Cancellation Finished 1 1 1 read-only CF10 Tx Buffer Cancellation Finished 10 10 1 read-only CF11 Tx Buffer Cancellation Finished 11 11 1 read-only CF12 Tx Buffer Cancellation Finished 12 12 1 read-only CF13 Tx Buffer Cancellation Finished 13 13 1 read-only CF14 Tx Buffer Cancellation Finished 14 14 1 read-only CF15 Tx Buffer Cancellation Finished 15 15 1 read-only CF16 Tx Buffer Cancellation Finished 16 16 1 read-only CF17 Tx Buffer Cancellation Finished 17 17 1 read-only CF18 Tx Buffer Cancellation Finished 18 18 1 read-only CF19 Tx Buffer Cancellation Finished 19 19 1 read-only CF2 Tx Buffer Cancellation Finished 2 2 1 read-only CF20 Tx Buffer Cancellation Finished 20 20 1 read-only CF21 Tx Buffer Cancellation Finished 21 21 1 read-only CF22 Tx Buffer Cancellation Finished 22 22 1 read-only CF23 Tx Buffer Cancellation Finished 23 23 1 read-only CF24 Tx Buffer Cancellation Finished 24 24 1 read-only CF25 Tx Buffer Cancellation Finished 25 25 1 read-only CF26 Tx Buffer Cancellation Finished 26 26 1 read-only CF27 Tx Buffer Cancellation Finished 27 27 1 read-only CF28 Tx Buffer Cancellation Finished 28 28 1 read-only CF29 Tx Buffer Cancellation Finished 29 29 1 read-only CF3 Tx Buffer Cancellation Finished 3 3 1 read-only CF30 Tx Buffer Cancellation Finished 30 30 1 read-only CF31 Tx Buffer Cancellation Finished 31 31 1 read-only CF4 Tx Buffer Cancellation Finished 4 4 1 read-only CF5 Tx Buffer Cancellation Finished 5 5 1 read-only CF6 Tx Buffer Cancellation Finished 6 6 1 read-only CF7 Tx Buffer Cancellation Finished 7 7 1 read-only CF8 Tx Buffer Cancellation Finished 8 8 1 read-only CF9 Tx Buffer Cancellation Finished 9 9 1 read-only TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 read-write n 0x0 0x0 CFIE0 Cancellation Finished Interrupt Enable 0 0 1 CFIE1 Cancellation Finished Interrupt Enable 1 1 1 CFIE10 Cancellation Finished Interrupt Enable 10 10 1 CFIE11 Cancellation Finished Interrupt Enable 11 11 1 CFIE12 Cancellation Finished Interrupt Enable 12 12 1 CFIE13 Cancellation Finished Interrupt Enable 13 13 1 CFIE14 Cancellation Finished Interrupt Enable 14 14 1 CFIE15 Cancellation Finished Interrupt Enable 15 15 1 CFIE16 Cancellation Finished Interrupt Enable 16 16 1 CFIE17 Cancellation Finished Interrupt Enable 17 17 1 CFIE18 Cancellation Finished Interrupt Enable 18 18 1 CFIE19 Cancellation Finished Interrupt Enable 19 19 1 CFIE2 Cancellation Finished Interrupt Enable 2 2 1 CFIE20 Cancellation Finished Interrupt Enable 20 20 1 CFIE21 Cancellation Finished Interrupt Enable 21 21 1 CFIE22 Cancellation Finished Interrupt Enable 22 22 1 CFIE23 Cancellation Finished Interrupt Enable 23 23 1 CFIE24 Cancellation Finished Interrupt Enable 24 24 1 CFIE25 Cancellation Finished Interrupt Enable 25 25 1 CFIE26 Cancellation Finished Interrupt Enable 26 26 1 CFIE27 Cancellation Finished Interrupt Enable 27 27 1 CFIE28 Cancellation Finished Interrupt Enable 28 28 1 CFIE29 Cancellation Finished Interrupt Enable 29 29 1 CFIE3 Cancellation Finished Interrupt Enable 3 3 1 CFIE30 Cancellation Finished Interrupt Enable 30 30 1 CFIE31 Cancellation Finished Interrupt Enable 31 31 1 CFIE4 Cancellation Finished Interrupt Enable 4 4 1 CFIE5 Cancellation Finished Interrupt Enable 5 5 1 CFIE6 Cancellation Finished Interrupt Enable 6 6 1 CFIE7 Cancellation Finished Interrupt Enable 7 7 1 CFIE8 Cancellation Finished Interrupt Enable 8 8 1 CFIE9 Cancellation Finished Interrupt Enable 9 9 1 TXBCR Tx Buffer Cancellation Request 0xD4 32 read-write n 0x0 0x0 CR0 Cancellation Request 0 0 1 CR1 Cancellation Request 1 1 1 CR10 Cancellation Request 10 10 1 CR11 Cancellation Request 11 11 1 CR12 Cancellation Request 12 12 1 CR13 Cancellation Request 13 13 1 CR14 Cancellation Request 14 14 1 CR15 Cancellation Request 15 15 1 CR16 Cancellation Request 16 16 1 CR17 Cancellation Request 17 17 1 CR18 Cancellation Request 18 18 1 CR19 Cancellation Request 19 19 1 CR2 Cancellation Request 2 2 1 CR20 Cancellation Request 20 20 1 CR21 Cancellation Request 21 21 1 CR22 Cancellation Request 22 22 1 CR23 Cancellation Request 23 23 1 CR24 Cancellation Request 24 24 1 CR25 Cancellation Request 25 25 1 CR26 Cancellation Request 26 26 1 CR27 Cancellation Request 27 27 1 CR28 Cancellation Request 28 28 1 CR29 Cancellation Request 29 29 1 CR3 Cancellation Request 3 3 1 CR30 Cancellation Request 30 30 1 CR31 Cancellation Request 31 31 1 CR4 Cancellation Request 4 4 1 CR5 Cancellation Request 5 5 1 CR6 Cancellation Request 6 6 1 CR7 Cancellation Request 7 7 1 CR8 Cancellation Request 8 8 1 CR9 Cancellation Request 9 9 1 TXBRP Tx Buffer Request Pending 0xCC 32 read-only n 0x0 0x0 TRP0 Transmission Request Pending 0 0 1 read-only TRP1 Transmission Request Pending 1 1 1 read-only TRP10 Transmission Request Pending 10 10 1 read-only TRP11 Transmission Request Pending 11 11 1 read-only TRP12 Transmission Request Pending 12 12 1 read-only TRP13 Transmission Request Pending 13 13 1 read-only TRP14 Transmission Request Pending 14 14 1 read-only TRP15 Transmission Request Pending 15 15 1 read-only TRP16 Transmission Request Pending 16 16 1 read-only TRP17 Transmission Request Pending 17 17 1 read-only TRP18 Transmission Request Pending 18 18 1 read-only TRP19 Transmission Request Pending 19 19 1 read-only TRP2 Transmission Request Pending 2 2 1 read-only TRP20 Transmission Request Pending 20 20 1 read-only TRP21 Transmission Request Pending 21 21 1 read-only TRP22 Transmission Request Pending 22 22 1 read-only TRP23 Transmission Request Pending 23 23 1 read-only TRP24 Transmission Request Pending 24 24 1 read-only TRP25 Transmission Request Pending 25 25 1 read-only TRP26 Transmission Request Pending 26 26 1 read-only TRP27 Transmission Request Pending 27 27 1 read-only TRP28 Transmission Request Pending 28 28 1 read-only TRP29 Transmission Request Pending 29 29 1 read-only TRP3 Transmission Request Pending 3 3 1 read-only TRP30 Transmission Request Pending 30 30 1 read-only TRP31 Transmission Request Pending 31 31 1 read-only TRP4 Transmission Request Pending 4 4 1 read-only TRP5 Transmission Request Pending 5 5 1 read-only TRP6 Transmission Request Pending 6 6 1 read-only TRP7 Transmission Request Pending 7 7 1 read-only TRP8 Transmission Request Pending 8 8 1 read-only TRP9 Transmission Request Pending 9 9 1 read-only TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 read-write n 0x0 0x0 TIE0 Transmission Interrupt Enable 0 0 1 TIE1 Transmission Interrupt Enable 1 1 1 TIE10 Transmission Interrupt Enable 10 10 1 TIE11 Transmission Interrupt Enable 11 11 1 TIE12 Transmission Interrupt Enable 12 12 1 TIE13 Transmission Interrupt Enable 13 13 1 TIE14 Transmission Interrupt Enable 14 14 1 TIE15 Transmission Interrupt Enable 15 15 1 TIE16 Transmission Interrupt Enable 16 16 1 TIE17 Transmission Interrupt Enable 17 17 1 TIE18 Transmission Interrupt Enable 18 18 1 TIE19 Transmission Interrupt Enable 19 19 1 TIE2 Transmission Interrupt Enable 2 2 1 TIE20 Transmission Interrupt Enable 20 20 1 TIE21 Transmission Interrupt Enable 21 21 1 TIE22 Transmission Interrupt Enable 22 22 1 TIE23 Transmission Interrupt Enable 23 23 1 TIE24 Transmission Interrupt Enable 24 24 1 TIE25 Transmission Interrupt Enable 25 25 1 TIE26 Transmission Interrupt Enable 26 26 1 TIE27 Transmission Interrupt Enable 27 27 1 TIE28 Transmission Interrupt Enable 28 28 1 TIE29 Transmission Interrupt Enable 29 29 1 TIE3 Transmission Interrupt Enable 3 3 1 TIE30 Transmission Interrupt Enable 30 30 1 TIE31 Transmission Interrupt Enable 31 31 1 TIE4 Transmission Interrupt Enable 4 4 1 TIE5 Transmission Interrupt Enable 5 5 1 TIE6 Transmission Interrupt Enable 6 6 1 TIE7 Transmission Interrupt Enable 7 7 1 TIE8 Transmission Interrupt Enable 8 8 1 TIE9 Transmission Interrupt Enable 9 9 1 TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only n 0x0 0x0 TO0 Transmission Occurred 0 0 1 read-only TO1 Transmission Occurred 1 1 1 read-only TO10 Transmission Occurred 10 10 1 read-only TO11 Transmission Occurred 11 11 1 read-only TO12 Transmission Occurred 12 12 1 read-only TO13 Transmission Occurred 13 13 1 read-only TO14 Transmission Occurred 14 14 1 read-only TO15 Transmission Occurred 15 15 1 read-only TO16 Transmission Occurred 16 16 1 read-only TO17 Transmission Occurred 17 17 1 read-only TO18 Transmission Occurred 18 18 1 read-only TO19 Transmission Occurred 19 19 1 read-only TO2 Transmission Occurred 2 2 1 read-only TO20 Transmission Occurred 20 20 1 read-only TO21 Transmission Occurred 21 21 1 read-only TO22 Transmission Occurred 22 22 1 read-only TO23 Transmission Occurred 23 23 1 read-only TO24 Transmission Occurred 24 24 1 read-only TO25 Transmission Occurred 25 25 1 read-only TO26 Transmission Occurred 26 26 1 read-only TO27 Transmission Occurred 27 27 1 read-only TO28 Transmission Occurred 28 28 1 read-only TO29 Transmission Occurred 29 29 1 read-only TO3 Transmission Occurred 3 3 1 read-only TO30 Transmission Occurred 30 30 1 read-only TO31 Transmission Occurred 31 31 1 read-only TO4 Transmission Occurred 4 4 1 read-only TO5 Transmission Occurred 5 5 1 read-only TO6 Transmission Occurred 6 6 1 read-only TO7 Transmission Occurred 7 7 1 read-only TO8 Transmission Occurred 8 8 1 read-only TO9 Transmission Occurred 9 9 1 read-only TXEFA Tx Event FIFO Acknowledge 0xF8 32 read-write n 0x0 0x0 EFAI Event FIFO Acknowledge Index 0 5 TXEFC Tx Event FIFO Configuration 0xF0 32 read-write n 0x0 0x0 EFS Event FIFO Size 16 6 EFSA Event FIFO Start Address 0 16 EFWM Event FIFO Watermark 24 6 TXEFS Tx Event FIFO Status 0xF4 32 read-only n 0x0 0x0 EFF Event FIFO Full 24 1 read-only EFFL Event FIFO Fill Level 0 6 read-only EFGI Event FIFO Get Index 8 5 read-only EFPI Event FIFO Put Index 16 5 read-only TEFL Tx Event FIFO Element Lost 25 1 read-only TXESC Tx Buffer Element Size Configuration 0xC8 32 read-write n 0x0 0x0 TBDS Tx Buffer Data Field Size 0 3 TBDSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 TXFQS Tx FIFO / Queue Status 0xC4 32 read-only n 0x0 0x0 TFFL Tx FIFO Free Level 0 6 read-only TFGI Tx FIFO Get Index 8 5 read-only TFQF Tx FIFO/Queue Full 21 1 read-only TFQPI Tx FIFO/Queue Put Index 16 5 read-only XIDAM Extended ID AND Mask 0x90 32 read-write n 0x0 0x0 EIDM Extended ID Mask 0 29 XIDFC Extended ID Filter Configuration 0x88 32 read-write n 0x0 0x0 FLESA Filter List Extended Start Address 0 16 LSE List Size Extended 16 7 CCL Configurable Custom Logic CCL 0x0 0x0 0x40 registers n 0x0 0x18 registers n CTRL Control 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only LUTCTRL0 LUT Control x 0x10 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 ALT2TC Alternate 2 TC input source 0xa ASYNCEVENT ASYNC EVENT input source. The EVENT input will bypass edge detection logic. 0xb INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL1 LUT Control x 0x1C 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 ALT2TC Alternate 2 TC input source 0xa ASYNCEVENT ASYNC EVENT input source. The EVENT input will bypass edge detection logic. 0xb INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL2 LUT Control x 0x2C 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 ALT2TC Alternate 2 TC input source 0xa ASYNCEVENT ASYNC EVENT input source. The EVENT input will bypass edge detection logic. 0xb INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL3 LUT Control x 0x40 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0x0 SYNCH Synchronizer enabled 0x1 FILTER Filter enabled 0x2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0x0 FEEDBACK Feedback input source 0x1 LINK Linked LUT input source 0x2 EVENT Event in put source 0x3 IO I/O pin input source 0x4 AC AC input source 0x5 TC TC input source 0x6 ALTTC Alternate TC input source 0x7 TCC TCC input source 0x8 SERCOM SERCOM inout source 0x9 ALT2TC Alternate 2 TC input source 0xa ASYNCEVENT ASYNC EVENT input source. The EVENT input will bypass edge detection logic. 0xb INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 SEQCTRL0 SEQ Control x 0x8 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0x0 DFF D flip flop 0x1 JK JK flip flop 0x2 LATCH D latch 0x3 RS RS latch 0x4 SEQCTRL1 SEQ Control x 0xD 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0x0 DFF D flip flop 0x1 JK JK flip flop 0x2 LATCH D latch 0x3 RS RS latch 0x4 DAC Digital Analog Converter DAC 0x0 0x0 0x20 registers n 0x0 0x15 registers n DAC_INTREQ 28 DAC 28 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0x0 DITHER Dither Enable 5 1 EOEN External Output Enable 0 1 IOEN Internal Output Enable 1 1 LEFTADJ Left Adjusted Data 2 1 REFSEL Reference Selection 6 2 REFSELSelect INT1V Internal 1.0V reference 0x0 AVCC AVCC 0x1 VREFP External reference 0x2 VPD Voltage Pump Disable 3 1 DATA Data 0x8 16 write-only n 0x0 0x0 DATA Data value to be converted 0 16 DATABUF Data Buffer 0xC 16 write-only n 0x0 0x0 DATABUF Data Buffer 0 16 DBGCTRL Debug Control 0x14 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 EMPTYEO Data Buffer Empty Event Output 1 1 INVEI Invert Event Input 2 1 STARTEI Start Conversion Event Input 0 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EMPTY Data Buffer Empty Interrupt Enable 1 1 UNDERRUN Underrun Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EMPTY Data Buffer Empty Interrupt Enable 1 1 UNDERRUN Underrun Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EMPTY Data Buffer Empty 1 1 UNDERRUN Underrun 0 1 STATUS Status 0x7 8 read-only n 0x0 0x0 READY Ready 0 1 read-only SYNCBUSY Synchronization Busy 0x10 32 read-only n 0x0 0x0 DATA Data 2 1 read-only DATABUF Data Buffer 3 1 read-only ENABLE Enable 1 1 read-only SWRST Software Reset 0 1 read-only DIVAS Divide and Square Root Accelerator DIVAS 0x0 0x0 0x20 registers n 0x0 0x1C registers n CTRLA Control 0x0 8 read-write n 0x0 0x0 DLZ Disable Leading Zero Optimization 1 1 SIGNED Signed 0 1 DIVIDEND Dividend 0x8 32 read-write n 0x0 0x0 DIVIDEND DIVIDEND 0 32 DIVISOR Divisor 0xC 32 read-write n 0x0 0x0 DIVISOR DIVISOR 0 32 REM Remainder 0x14 32 read-only n 0x0 0x0 REM REM 0 32 read-only RESULT Result 0x10 32 read-only n 0x0 0x0 RESULT RESULT 0 32 read-only SQRNUM Square Root Input 0x18 32 read-write n 0x0 0x0 SQRNUM Square Root Input 0 32 STATUS Status 0x4 8 read-write n 0x0 0x0 BUSY DIVAS Accelerator Busy 0 1 read-only DBZ Writing a one to this bit clears DBZ to zero 1 1 DIVAS_IOBUS Divide and Square Root Accelerator (IOBUS) DIVAS 0x0 0x0 0x20 registers n 0x0 0x1C registers n CTRLA Control 0x0 8 read-write n 0x0 0x0 DLZ Disable Leading Zero Optimization 1 1 SIGNED Signed 0 1 DIVIDEND Dividend 0x8 32 read-write n 0x0 0x0 DIVIDEND DIVIDEND 0 32 DIVISOR Divisor 0xC 32 read-write n 0x0 0x0 DIVISOR DIVISOR 0 32 REM Remainder 0x14 32 read-only n 0x0 0x0 REM REM 0 32 read-only RESULT Result 0x10 32 read-only n 0x0 0x0 RESULT RESULT 0 32 read-only SQRNUM Square Root Input 0x18 32 read-write n 0x0 0x0 SQRNUM Square Root Input 0 32 STATUS Status 0x4 8 read-write n 0x0 0x0 BUSY DIVAS Accelerator Busy 0 1 read-only DBZ Writing a one to this bit clears DBZ to zero 1 1 DMAC Direct Memory Access Controller DMAC 0x0 0x0 0x2C registers n 0x0 0x50 registers n DMAC_INTREQ 7 DMAC 7 ACTIVE Active Channel and Levels 0x30 32 read-only n 0x0 0x0 ABUSY Active Channel Busy 15 1 read-only BTCNT Active Channel Block Transfer Count 16 16 read-only ID Active Channel ID 8 5 read-only LVLEX0 Level 0 Channel Trigger Request Executing 0 1 read-only LVLEX1 Level 1 Channel Trigger Request Executing 1 1 read-only LVLEX2 Level 2 Channel Trigger Request Executing 2 1 read-only LVLEX3 Level 3 Channel Trigger Request Executing 3 1 read-only BASEADDR Descriptor Memory Section Base Address 0x34 32 read-write n 0x0 0x0 BASEADDR Descriptor Memory Base Address 0 32 BUSYCH Busy Channels 0x28 32 read-only n 0x0 0x0 BUSYCH0 Busy Channel 0 0 1 read-only BUSYCH1 Busy Channel 1 1 1 read-only BUSYCH10 Busy Channel 10 10 1 read-only BUSYCH11 Busy Channel 11 11 1 read-only BUSYCH2 Busy Channel 2 2 1 read-only BUSYCH3 Busy Channel 3 3 1 read-only BUSYCH4 Busy Channel 4 4 1 read-only BUSYCH5 Busy Channel 5 5 1 read-only BUSYCH6 Busy Channel 6 6 1 read-only BUSYCH7 Busy Channel 7 7 1 read-only BUSYCH8 Busy Channel 8 8 1 read-only BUSYCH9 Busy Channel 9 9 1 read-only CHCTRLA Channel Control A 0x40 8 read-write n 0x0 0x0 ENABLE Channel Enable 1 1 RUNSTDBY Channel run in standby 6 1 SWRST Channel Software Reset 0 1 CHCTRLB Channel Control B 0x44 32 read-write n 0x0 0x0 CMD Software Command 24 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 EVACT Event Input Action 0 3 EVACTSelect NOACT No action 0x0 TRIG Transfer and periodic transfer trigger 0x1 CTRIG Conditional transfer trigger 0x2 CBLOCK Conditional block transfer 0x3 SUSPEND Channel suspend operation 0x4 RESUME Channel resume operation 0x5 SSKIP Skip next block suspend action 0x6 EVIE Channel Event Input Enable 3 1 EVOE Channel Event Output Enable 4 1 LVL Channel Arbitration Level 5 2 TRIGACT Trigger Action 22 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0x0 BEAT One trigger required for each beat transfer 0x2 TRANSACTION One trigger required for each transaction 0x3 TRIGSRC Trigger Source 8 6 TRIGSRCSelect DISABLE Only software/event triggers 0x0 CHID Channel ID 0x3F 8 read-write n 0x0 0x0 ID Channel ID 0 4 CHINTENCLR Channel Interrupt Enable Clear 0x4C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHINTENSET Channel Interrupt Enable Set 0x4D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHINTFLAG Channel Interrupt Flag Status and Clear 0x4E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHSTATUS Channel Status 0x4F 8 read-only n 0x0 0x0 BUSY Channel Busy 1 1 read-only FERR Channel Fetch Error 2 1 read-only PEND Channel Pending 0 1 read-only CRCCHKSUM CRC Checksum 0x8 32 read-write n 0x0 0x0 CRCCHKSUM CRC Checksum 0 32 CRCCTRL CRC Control 0x2 16 read-write n 0x0 0x0 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE 8-bit bus transfer 0x0 HWORD 16-bit bus transfer 0x1 WORD 32-bit bus transfer 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect NOACT No action 0x0 IO I/O interface 0x1 CRCDATAIN CRC Data Input 0x4 32 read-write n 0x0 0x0 CRCDATAIN CRC Data Input 0 32 CRCSTATUS CRC Status 0xC 8 read-write n 0x0 0x0 CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 read-only CTRL Control 0x0 16 read-write n 0x0 0x0 CRCENABLE CRC Enable 2 1 DMAENABLE DMA Enable 1 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 SWRST Software Reset 0 1 DBGCTRL Debug Control 0xD 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 INTPEND Interrupt Pending 0x20 16 read-write n 0x0 0x0 BUSY Busy 14 1 read-only FERR Fetch Error 13 1 read-only ID Channel ID 0 4 PEND Pending 15 1 read-only SUSP Channel Suspend 10 1 TCMPL Transfer Complete 9 1 TERR Transfer Error 8 1 INTSTATUS Interrupt Status 0x24 32 read-only n 0x0 0x0 CHINT0 Channel 0 Pending Interrupt 0 1 read-only CHINT1 Channel 1 Pending Interrupt 1 1 read-only CHINT10 Channel 10 Pending Interrupt 10 1 read-only CHINT11 Channel 11 Pending Interrupt 11 1 read-only CHINT2 Channel 2 Pending Interrupt 2 1 read-only CHINT3 Channel 3 Pending Interrupt 3 1 read-only CHINT4 Channel 4 Pending Interrupt 4 1 read-only CHINT5 Channel 5 Pending Interrupt 5 1 read-only CHINT6 Channel 6 Pending Interrupt 6 1 read-only CHINT7 Channel 7 Pending Interrupt 7 1 read-only CHINT8 Channel 8 Pending Interrupt 8 1 read-only CHINT9 Channel 9 Pending Interrupt 9 1 read-only PENDCH Pending Channels 0x2C 32 read-only n 0x0 0x0 PENDCH0 Pending Channel 0 0 1 read-only PENDCH1 Pending Channel 1 1 1 read-only PENDCH10 Pending Channel 10 10 1 read-only PENDCH11 Pending Channel 11 11 1 read-only PENDCH2 Pending Channel 2 2 1 read-only PENDCH3 Pending Channel 3 3 1 read-only PENDCH4 Pending Channel 4 4 1 read-only PENDCH5 Pending Channel 5 5 1 read-only PENDCH6 Pending Channel 6 6 1 read-only PENDCH7 Pending Channel 7 7 1 read-only PENDCH8 Pending Channel 8 8 1 read-only PENDCH9 Pending Channel 9 9 1 read-only PRICTRL0 Priority Control 0 0x14 32 read-write n 0x0 0x0 LVLPRI0 Level 0 Channel Priority Number 0 4 LVLPRI1 Level 1 Channel Priority Number 8 4 LVLPRI2 Level 2 Channel Priority Number 16 4 LVLPRI3 Level 3 Channel Priority Number 24 4 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 QOSCTRL QOS Control 0xE 8 read-write n 0x0 0x0 DQOS Data Transfer Quality of Service 4 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 FQOS Fetch Quality of Service 2 2 FQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 WRBQOS Write-Back Quality of Service 0 2 WRBQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 SWTRIGCTRL Software Trigger Control 0x10 32 read-write n 0x0 0x0 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 WRBADDR Write-Back Memory Section Base Address 0x38 32 read-write n 0x0 0x0 WRBADDR Write-Back Memory Base Address 0 32 DSU Device Service Unit DSU 0x0 0x0 0x2000 registers n ADDR Address 0x4 32 read-write n 0x0 0x0 ADDR Address 2 30 AMOD Access Mode 0 2 CID0 Component Identification 0 0x1FF0 32 read-only n 0x0 0x0 PREAMBLEB0 Preamble Byte 0 0 8 read-only CID1 Component Identification 1 0x1FF4 32 read-only n 0x0 0x0 CCLASS Component Class 4 4 read-only PREAMBLE Preamble 0 4 read-only CID2 Component Identification 2 0x1FF8 32 read-only n 0x0 0x0 PREAMBLEB2 Preamble Byte 2 0 8 read-only CID3 Component Identification 3 0x1FFC 32 read-only n 0x0 0x0 PREAMBLEB3 Preamble Byte 3 0 8 CTRL Control 0x0 8 write-only n 0x0 0x0 ARR Auxiliary Row Read 6 1 write-only CE Chip-Erase 4 1 write-only CRC 32-bit Cyclic Redundancy Code 2 1 write-only MBIST Memory built-in self-test 3 1 write-only SMSA Start Memory Stream Access 7 1 write-only SWRST Software Reset 0 1 write-only DATA Data 0xC 32 read-write n 0x0 0x0 DATA Data 0 32 DCC0 Debug Communication Channel n 0x20 32 read-write n 0x0 0x0 DATA Data 0 32 DCC1 Debug Communication Channel n 0x34 32 read-write n 0x0 0x0 DATA Data 0 32 DCFG0 Device Configuration 0x1E0 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DCFG1 Device Configuration 0x2D4 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DID Device Identification 0x18 32 read-only n 0x0 0x0 DEVSEL Device Select 0 8 read-only DIE Die Number 12 4 read-only FAMILY Family 23 5 read-only FAMILYSelect 0 General purpose microcontroller 0x0 1 PicoPower 0x1 2 5V Industrial 0x2 PROCESSOR Processor 28 4 read-only PROCESSORSelect 0 Cortex-M0 0x0 1 Cortex-M0+ 0x1 2 Cortex-M3 0x2 3 Cortex-M4 0x3 REVISION Revision Number 8 4 read-only SERIES Series 16 6 read-only SERIESSelect 0 Cortex-M0+ processor, basic feature set 0x0 1 Cortex-M0+ processor, USB 0x1 END CoreSight ROM Table End 0x1008 32 read-only n 0x0 0x0 END End Marker 0 32 ENTRY0 CoreSight ROM Table Entry 0 0x1000 32 read-only n 0x0 0x0 ADDOFF Address Offset 12 20 read-only EPRES Entry Present 0 1 FMT Format 1 1 read-only ENTRY1 CoreSight ROM Table Entry 1 0x1004 32 read-only n 0x0 0x0 LENGTH Length 0x8 32 read-write n 0x0 0x0 LENGTH Length 2 30 MEMTYPE CoreSight ROM Table Memory Type 0x1FCC 32 read-only n 0x0 0x0 SMEMP System Memory Present 0 1 PID0 Peripheral Identification 0 0x1FE0 32 read-only n 0x0 0x0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only n 0x0 0x0 JEPIDCL Low part of the JEP-106 Identity Code 4 4 read-only PARTNBH Part Number High 0 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only n 0x0 0x0 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 read-only REVISION Revision Number 4 4 read-only PID3 Peripheral Identification 3 0x1FEC 32 read-only n 0x0 0x0 CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 read-only PID4 Peripheral Identification 4 0x1FD0 32 read-only n 0x0 0x0 FKBC 4KB count 4 4 read-only JEPCC JEP-106 Continuation Code 0 4 PID5 Peripheral Identification 5 0x1FD4 32 read-only n 0x0 0x0 PID6 Peripheral Identification 6 0x1FD8 32 read-only n 0x0 0x0 PID7 Peripheral Identification 7 0x1FDC 32 read-only n 0x0 0x0 STATUSA Status A 0x1 8 read-write n 0x0 0x0 BERR Bus Error 2 1 CRSTEXT CPU Reset Phase Extension 1 1 DONE Done 0 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x2 8 read-only n 0x0 0x0 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 PROT Protected 0 1 EIC External Interrupt Controller EIC 0x0 0x0 0x40 registers n 0x0 0x3C registers n EIC_INTREQ 3 EIC 3 ASYNCH External Interrupt Asynchronous Mode 0x18 32 read-write n 0x0 0x0 ASYNCH Asynchronous Edge Detection Mode 0 16 CONFIG0 External Interrupt Sense Configuration 0x38 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CONFIG1 External Interrupt Sense Configuration 0x58 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 CTRLA Control A 0x0 8 read-write n 0x0 0x0 CKSEL Clock Selection 4 1 ENABLE Enable 1 1 SWRST Software Reset 0 1 write-only DEBOUNCEN Debouncer Enable 0x30 32 read-write n 0x0 0x0 DEBOUNCEN Debouncer Enable 0 16 DPRESCALER Debouncer Prescaler 0x34 32 read-write n 0x0 0x0 PRESCALER0 Debouncer Prescaler 0 3 PRESCALER1 Debouncer Prescaler 4 3 STATES0 Debouncer number of states 3 1 STATES1 Debouncer number of states 7 1 TICKON Pin Sampler frequency selection 16 1 EVCTRL Event Control 0x8 32 read-write n 0x0 0x0 EXTINTEO External Interrupt Event Output Enable 0 16 INTENCLR Interrupt Enable Clear 0xC 32 read-write n 0x0 0x0 EXTINT External Interrupt Enable 0 16 INTENSET Interrupt Enable Set 0x10 32 read-write n 0x0 0x0 EXTINT External Interrupt Enable 0 16 INTFLAG Interrupt Flag Status and Clear 0x14 32 read-write n 0x0 0x0 EXTINT External Interrupt 0 16 NMICTRL Non-Maskable Interrupt Control 0x1 8 read-write n 0x0 0x0 NMIASYNCH Asynchronous Edge Detection Mode 4 1 NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMISENSE Non-Maskable Interrupt Sense Configuration 0 3 NMISENSESelect NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x2 16 read-write n 0x0 0x0 NMI Non-Maskable Interrupt 0 1 PINSTATE Pin State 0x38 32 read-only n 0x0 0x0 PINSTATE Pin State 0 16 read-only SYNCBUSY Synchronization Busy 0x4 32 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy Status 1 1 read-only SWRST Software Reset Synchronization Busy Status 0 1 read-only EVSYS Event System Interface EVSYS 0x0 0x0 0x400 registers n 0x0 0x1C0 registers n EVSYS_INTREQ 8 EVSYS 8 CHANNEL0 Channel n 0x40 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL1 Channel n 0x64 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL10 Channel n 0x25C 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL11 Channel n 0x2A8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL2 Channel n 0x8C 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL3 Channel n 0xB8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL4 Channel n 0xE8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL5 Channel n 0x11C 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL6 Channel n 0x154 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL7 Channel n 0x190 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL8 Channel n 0x1D0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHANNEL9 Channel n 0x214 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 RUNSTDBY Run in standby 14 1 CHSTATUS Channel Status 0xC 32 read-only n 0x0 0x0 CHBUSY0 Channel 0 Busy 16 1 read-only CHBUSY1 Channel 1 Busy 17 1 read-only CHBUSY10 Channel 10 Busy 26 1 read-only CHBUSY11 Channel 11 Busy 27 1 read-only CHBUSY2 Channel 2 Busy 18 1 read-only CHBUSY3 Channel 3 Busy 19 1 read-only CHBUSY4 Channel 4 Busy 20 1 read-only CHBUSY5 Channel 5 Busy 21 1 read-only CHBUSY6 Channel 6 Busy 22 1 read-only CHBUSY7 Channel 7 Busy 23 1 read-only CHBUSY8 Channel 8 Busy 24 1 read-only CHBUSY9 Channel 9 Busy 25 1 read-only USRRDY0 Channel 0 User Ready 0 1 read-only USRRDY1 Channel 1 User Ready 1 1 read-only USRRDY10 Channel 10 User Ready 10 1 read-only USRRDY11 Channel 11 User Ready 11 1 read-only USRRDY2 Channel 2 User Ready 2 1 read-only USRRDY3 Channel 3 User Ready 3 1 read-only USRRDY4 Channel 4 User Ready 4 1 read-only USRRDY5 Channel 5 User Ready 5 1 read-only USRRDY6 Channel 6 User Ready 6 1 read-only USRRDY7 Channel 7 User Ready 7 1 read-only USRRDY8 Channel 8 User Ready 8 1 read-only USRRDY9 Channel 9 User Ready 9 1 read-only CTRLA Control 0x0 8 read-write n 0x0 0x0 SWRST Software Reset 0 1 write-only INTENCLR Interrupt Enable Clear 0x10 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 INTENSET Interrupt Enable Set 0x14 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 INTFLAG Interrupt Flag Status and Clear 0x18 32 read-write n 0x0 0x0 EVD0 Channel 0 Event Detection 16 1 EVD1 Channel 1 Event Detection 17 1 EVD10 Channel 10 Event Detection 26 1 EVD11 Channel 11 Event Detection 27 1 EVD2 Channel 2 Event Detection 18 1 EVD3 Channel 3 Event Detection 19 1 EVD4 Channel 4 Event Detection 20 1 EVD5 Channel 5 Event Detection 21 1 EVD6 Channel 6 Event Detection 22 1 EVD7 Channel 7 Event Detection 23 1 EVD8 Channel 8 Event Detection 24 1 EVD9 Channel 9 Event Detection 25 1 OVR0 Channel 0 Overrun 0 1 OVR1 Channel 1 Overrun 1 1 OVR10 Channel 10 Overrun 10 1 OVR11 Channel 11 Overrun 11 1 OVR2 Channel 2 Overrun 2 1 OVR3 Channel 3 Overrun 3 1 OVR4 Channel 4 Overrun 4 1 OVR5 Channel 5 Overrun 5 1 OVR6 Channel 6 Overrun 6 1 OVR7 Channel 7 Overrun 7 1 OVR8 Channel 8 Overrun 8 1 OVR9 Channel 9 Overrun 9 1 SWEVT Software Event 0x1C 32 write-only n 0x0 0x0 CHANNEL0 Channel 0 Software Selection 0 1 CHANNEL1 Channel 1 Software Selection 1 1 CHANNEL10 Channel 10 Software Selection 10 1 CHANNEL11 Channel 11 Software Selection 11 1 CHANNEL2 Channel 2 Software Selection 2 1 CHANNEL3 Channel 3 Software Selection 3 1 CHANNEL4 Channel 4 Software Selection 4 1 CHANNEL5 Channel 5 Software Selection 5 1 CHANNEL6 Channel 6 Software Selection 6 1 CHANNEL7 Channel 7 Software Selection 7 1 CHANNEL8 Channel 8 Software Selection 8 1 CHANNEL9 Channel 9 Software Selection 9 1 USER0 User Multiplexer n 0x100 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER1 User Multiplexer n 0x184 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER10 User Multiplexer n 0x6DC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER11 User Multiplexer n 0x788 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER12 User Multiplexer n 0x838 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER13 User Multiplexer n 0x8EC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER14 User Multiplexer n 0x9A4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER15 User Multiplexer n 0xA60 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER16 User Multiplexer n 0xB20 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER17 User Multiplexer n 0xBE4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER18 User Multiplexer n 0xCAC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER19 User Multiplexer n 0xD78 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER2 User Multiplexer n 0x20C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER20 User Multiplexer n 0xE48 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER21 User Multiplexer n 0xF1C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER22 User Multiplexer n 0xFF4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER23 User Multiplexer n 0x10D0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER24 User Multiplexer n 0x11B0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER25 User Multiplexer n 0x1294 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER26 User Multiplexer n 0x137C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER27 User Multiplexer n 0x1468 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER28 User Multiplexer n 0x1558 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER29 User Multiplexer n 0x164C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER3 User Multiplexer n 0x298 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER30 User Multiplexer n 0x1744 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER31 User Multiplexer n 0x1840 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER32 User Multiplexer n 0x1940 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER33 User Multiplexer n 0x1A44 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER34 User Multiplexer n 0x1B4C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER35 User Multiplexer n 0x1C58 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER36 User Multiplexer n 0x1D68 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER37 User Multiplexer n 0x1E7C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER38 User Multiplexer n 0x1F94 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER39 User Multiplexer n 0x20B0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER4 User Multiplexer n 0x328 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER40 User Multiplexer n 0x21D0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER41 User Multiplexer n 0x22F4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER42 User Multiplexer n 0x241C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER43 User Multiplexer n 0x2548 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER44 User Multiplexer n 0x2678 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER45 User Multiplexer n 0x27AC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER46 User Multiplexer n 0x28E4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER47 User Multiplexer n 0x2A20 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER48 User Multiplexer n 0x2B60 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER49 User Multiplexer n 0x2CA4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER5 User Multiplexer n 0x3BC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER6 User Multiplexer n 0x454 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER7 User Multiplexer n 0x4F0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER8 User Multiplexer n 0x590 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 USER9 User Multiplexer n 0x634 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 5 FREQM Frequency Meter FREQM 0x0 0x0 0x20 registers n 0x0 0x14 registers n FREQM_INTREQ 4 FREQM 4 CFGA Config A register 0x2 16 read-write n 0x0 0x0 DIVREF Divide Reference Clock 15 1 REFNUM Number of Reference Clock Cycles 0 8 CTRLA Control A Register 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 CTRLB Control B Register 0x1 8 write-only n 0x0 0x0 START Start Measurement 0 1 write-only INTENCLR Interrupt Enable Clear Register 0x8 8 read-write n 0x0 0x0 DONE Measurement Done Interrupt Enable 0 1 INTENSET Interrupt Enable Set Register 0x9 8 read-write n 0x0 0x0 DONE Measurement Done Interrupt Enable 0 1 INTFLAG Interrupt Flag Register 0xA 8 read-write n 0x0 0x0 DONE Measurement Done 0 1 STATUS Status Register 0xB 8 read-write n 0x0 0x0 BUSY FREQM Status 0 1 read-only OVF Sticky Count Value Overflow 1 1 SYNCBUSY Synchronization Busy Register 0xC 32 read-only n 0x0 0x0 ENABLE Enable 1 1 read-only SWRST Software Reset 0 1 read-only VALUE Count Value Register 0x10 32 read-only n 0x0 0x0 VALUE Measurement Value 0 24 read-only GCLK Generic Clock Generator GCLK 0x0 0x0 0x200 registers n 0x0 0x198 registers n CTRLA Control 0x0 8 read-write n 0x0 0x0 SWRST Software Reset 0 1 GENCTRL0 Generic Clock Generator Control 0x40 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL1 Generic Clock Generator Control 0x64 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL2 Generic Clock Generator Control 0x8C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL3 Generic Clock Generator Control 0xB8 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL4 Generic Clock Generator Control 0xE8 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL5 Generic Clock Generator Control 0x11C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL6 Generic Clock Generator Control 0x154 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL7 Generic Clock Generator Control 0x190 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 GENCTRL8 Generic Clock Generator Control 0x1D0 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC48M OSC48M oscillator output 0x6 DPLL96M DPLL96M output 0x7 PCHCTRL0 Peripheral Clock Control 0x100 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL1 Peripheral Clock Control 0x184 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL10 Peripheral Clock Control 0x6DC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL11 Peripheral Clock Control 0x788 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL12 Peripheral Clock Control 0x838 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL13 Peripheral Clock Control 0x8EC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL14 Peripheral Clock Control 0x9A4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL15 Peripheral Clock Control 0xA60 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL16 Peripheral Clock Control 0xB20 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL17 Peripheral Clock Control 0xBE4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL18 Peripheral Clock Control 0xCAC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL19 Peripheral Clock Control 0xD78 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL2 Peripheral Clock Control 0x20C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL20 Peripheral Clock Control 0xE48 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL21 Peripheral Clock Control 0xF1C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL22 Peripheral Clock Control 0xFF4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL23 Peripheral Clock Control 0x10D0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL24 Peripheral Clock Control 0x11B0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL25 Peripheral Clock Control 0x1294 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL26 Peripheral Clock Control 0x137C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL27 Peripheral Clock Control 0x1468 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL28 Peripheral Clock Control 0x1558 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL29 Peripheral Clock Control 0x164C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL3 Peripheral Clock Control 0x298 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL30 Peripheral Clock Control 0x1744 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL31 Peripheral Clock Control 0x1840 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL32 Peripheral Clock Control 0x1940 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL33 Peripheral Clock Control 0x1A44 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL34 Peripheral Clock Control 0x1B4C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL35 Peripheral Clock Control 0x1C58 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL36 Peripheral Clock Control 0x1D68 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL37 Peripheral Clock Control 0x1E7C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL38 Peripheral Clock Control 0x1F94 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL39 Peripheral Clock Control 0x20B0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL4 Peripheral Clock Control 0x328 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL40 Peripheral Clock Control 0x21D0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL41 Peripheral Clock Control 0x22F4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL42 Peripheral Clock Control 0x241C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL43 Peripheral Clock Control 0x2548 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL44 Peripheral Clock Control 0x2678 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL45 Peripheral Clock Control 0x27AC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL5 Peripheral Clock Control 0x3BC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL6 Peripheral Clock Control 0x454 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL7 Peripheral Clock Control 0x4F0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL8 Peripheral Clock Control 0x590 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 PCHCTRL9 Peripheral Clock Control 0x634 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 WRTLOCK Write Lock 7 1 SYNCBUSY Synchronization Busy 0x4 32 read-only n 0x0 0x0 GENCTRL0 Generic Clock Generator Control 0 Synchronization Busy bits 2 1 read-only GENCTRL0Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL1 Generic Clock Generator Control 1 Synchronization Busy bits 3 1 read-only GENCTRL1Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL2 Generic Clock Generator Control 2 Synchronization Busy bits 4 1 read-only GENCTRL2Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL3 Generic Clock Generator Control 3 Synchronization Busy bits 5 1 read-only GENCTRL3Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL4 Generic Clock Generator Control 4 Synchronization Busy bits 6 1 read-only GENCTRL4Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL5 Generic Clock Generator Control 5 Synchronization Busy bits 7 1 read-only GENCTRL5Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL6 Generic Clock Generator Control 6 Synchronization Busy bits 8 1 read-only GENCTRL6Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL7 Generic Clock Generator Control 7 Synchronization Busy bits 9 1 read-only GENCTRL7Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 GENCTRL8 Generic Clock Generator Control 8 Synchronization Busy bits 10 1 read-only GENCTRL8Select GCLK0 Generic clock generator 0 0x1 GCLK4 Generic clock generator 4 0x10 GCLK8 Generic clock generator 8 0x100 GCLK1 Generic clock generator 1 0x2 GCLK5 Generic clock generator 5 0x20 GCLK2 Generic clock generator 2 0x4 GCLK6 Generic clock generator 6 0x40 GCLK3 Generic clock generator 3 0x8 GCLK7 Generic clock generator 7 0x80 SWRST Software Reset Synchroniation Busy bit 0 1 read-only HMATRIXHS HSB Matrix HMATRIXB 0x0 0x0 0x168 registers n HMATRIXB_MCFG0 Master Configuration 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG1 Master Configuration 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG10 Master Configuration 0xDC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG11 Master Configuration 0x108 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG12 Master Configuration 0x138 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG13 Master Configuration 0x16C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG14 Master Configuration 0x1A4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG15 Master Configuration 0x1E0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG2 Master Configuration 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG3 Master Configuration 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG4 Master Configuration 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG5 Master Configuration 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG6 Master Configuration 0x54 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG7 Master Configuration 0x70 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG8 Master Configuration 0x90 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MCFG9 Master Configuration 0xB4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0x0 SINGLE Single Access 0x1 FOUR_BEAT Four Beat Burst 0x2 EIGHT_BEAT Eight Beat Burst 0x3 SIXTEEN_BEAT Sixteen Beat Burst 0x4 HMATRIXB_MRCR Master Remap Control 0x100 32 read-write n 0x0 0x0 RCB0 Remap Command Bit for Master 0 0 1 RCB0Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB1 Remap Command Bit for Master 1 1 1 RCB1Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB10 Remap Command Bit for Master 10 10 1 RCB10Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB11 Remap Command Bit for Master 11 11 1 RCB11Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB12 Remap Command Bit for Master 12 12 1 RCB12Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB13 Remap Command Bit for Master 13 13 1 RCB13Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB14 Remap Command Bit for Master 14 14 1 RCB14Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB15 Remap Command Bit for Master 15 15 1 RCB15Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB2 Remap Command Bit for Master 2 2 1 RCB2Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB3 Remap Command Bit for Master 3 3 1 RCB3Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB4 Remap Command Bit for Master 4 4 1 RCB4Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB5 Remap Command Bit for Master 5 5 1 RCB5Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB6 Remap Command Bit for Master 6 6 1 RCB6Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB7 Remap Command Bit for Master 7 7 1 RCB7Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB8 Remap Command Bit for Master 8 8 1 RCB8Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 RCB9 Remap Command Bit for Master 9 9 1 RCB9Select DIS Disable remapped address decoding for master 0x0 ENA Enable remapped address decoding for master 0x1 HMATRIXB_PRAS0 Priority A for Slave 0x100 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS1 Priority A for Slave 0x188 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS2 Priority A for Slave 0x218 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRAS3 Priority A for Slave 0x2B0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 HMATRIXB_PRBS0 Priority B for Slave 0x108 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS1 Priority B for Slave 0x194 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS2 Priority B for Slave 0x228 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_PRBS3 Priority B for Slave 0x2C4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 HMATRIXB_SCFG0 Slave Configuration 0x80 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG1 Slave Configuration 0xC4 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG10 Slave Configuration 0x3DC 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG11 Slave Configuration 0x448 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG12 Slave Configuration 0x4B8 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG13 Slave Configuration 0x52C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG14 Slave Configuration 0x5A4 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG15 Slave Configuration 0x620 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG2 Slave Configuration 0x10C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG3 Slave Configuration 0x158 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG4 Slave Configuration 0x1A8 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG5 Slave Configuration 0x1FC 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG6 Slave Configuration 0x254 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG7 Slave Configuration 0x2B0 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG8 Slave Configuration 0x310 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SCFG9 Slave Configuration 0x374 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0x0 FIXED_PRIORITY Fixed Priority Arbitration 0x1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0x0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 0x1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 0x2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 HMATRIXB_SFR0 Special Function 0x220 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR1 Special Function 0x334 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR10 Special Function 0xD9C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR11 Special Function 0xED8 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR12 Special Function 0x1018 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR13 Special Function 0x115C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR14 Special Function 0x12A4 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR15 Special Function 0x13F0 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR2 Special Function 0x44C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR3 Special Function 0x568 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR4 Special Function 0x688 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR5 Special Function 0x7AC 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR6 Special Function 0x8D4 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR7 Special Function 0xA00 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR8 Special Function 0xB30 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 HMATRIXB_SFR9 Special Function 0xC64 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 MCFG0 Master Configuration 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG1 Master Configuration 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG10 Master Configuration 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG11 Master Configuration 0x2C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG12 Master Configuration 0x30 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG13 Master Configuration 0x34 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG14 Master Configuration 0x38 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG15 Master Configuration 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG2 Master Configuration 0x8 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG3 Master Configuration 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG4 Master Configuration 0x10 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG5 Master Configuration 0x14 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG6 Master Configuration 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG7 Master Configuration 0x1C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG8 Master Configuration 0x20 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MCFG9 Master Configuration 0x24 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 MRCR Master Remap Control 0x100 32 read-write n 0x0 0x0 RCB0 Remap Command Bit for Master 0 0 1 RCB0Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB1 Remap Command Bit for Master 1 1 1 RCB1Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB10 Remap Command Bit for Master 10 10 1 RCB10Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB11 Remap Command Bit for Master 11 11 1 RCB11Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB12 Remap Command Bit for Master 12 12 1 RCB12Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB13 Remap Command Bit for Master 13 13 1 RCB13Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB14 Remap Command Bit for Master 14 14 1 RCB14Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB15 Remap Command Bit for Master 15 15 1 RCB15Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB2 Remap Command Bit for Master 2 2 1 RCB2Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB3 Remap Command Bit for Master 3 3 1 RCB3Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB4 Remap Command Bit for Master 4 4 1 RCB4Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB5 Remap Command Bit for Master 5 5 1 RCB5Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB6 Remap Command Bit for Master 6 6 1 RCB6Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB7 Remap Command Bit for Master 7 7 1 RCB7Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB8 Remap Command Bit for Master 8 8 1 RCB8Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB9 Remap Command Bit for Master 9 9 1 RCB9Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 PRAS Priority A for Slave 0x0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS0 Priority A for Slave 0x80 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS1 Priority A for Slave 0x88 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS2 Priority A for Slave 0x90 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRAS3 Priority A for Slave 0x98 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRBS Priority B for Slave 0x4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS0 Priority B for Slave 0x84 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS1 Priority B for Slave 0x8C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS2 Priority B for Slave 0x94 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 PRBS3 Priority B for Slave 0x9C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 SCFG0 Slave Configuration 0x40 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG1 Slave Configuration 0x44 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG10 Slave Configuration 0x68 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG11 Slave Configuration 0x6C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG12 Slave Configuration 0x70 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG13 Slave Configuration 0x74 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG14 Slave Configuration 0x78 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG15 Slave Configuration 0x7C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG2 Slave Configuration 0x48 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG3 Slave Configuration 0x4C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG4 Slave Configuration 0x50 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG5 Slave Configuration 0x54 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG6 Slave Configuration 0x58 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG7 Slave Configuration 0x5C 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG8 Slave Configuration 0x60 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SCFG9 Slave Configuration 0x64 32 read-write n 0x0 0x0 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 SFR0 Special Function 0x110 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR1 Special Function 0x114 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR10 Special Function 0x138 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR11 Special Function 0x13C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR12 Special Function 0x140 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR13 Special Function 0x144 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR14 Special Function 0x148 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR15 Special Function 0x14C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR2 Special Function 0x118 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR3 Special Function 0x11C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR4 Special Function 0x120 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR5 Special Function 0x124 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR6 Special Function 0x128 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR7 Special Function 0x12C 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR8 Special Function 0x130 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 SFR9 Special Function 0x134 32 read-write n 0x0 0x0 SFR Special Function Register 0 32 MCLK Main Clock MCLK 0x0 0x0 0x2C registers n 0x0 0x24 registers n SYSTEM_INTREQ 0 AHBMASK AHB Mask 0x10 32 read-write n 0x0 0x0 CAN0_ CAN0 AHB Clock Mask 8 1 CAN1_ CAN1 AHB Clock Mask 9 1 DIVAS_ DIVAS AHB Clock Mask 12 1 DMAC_ DMAC AHB Clock Mask 7 1 DSU_ DSU AHB Clock Mask 3 1 HMATRIXHS_ HMATRIXHS AHB Clock Mask 4 1 HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 HPB3_ HPB3 AHB Clock Mask 13 1 HSRAM_ HSRAM AHB Clock Mask 6 1 NVMCTRL_ NVMCTRL AHB Clock Mask 5 1 NVMCTRL_PICACHU_ NVMCTRL_PICACHU AHB Clock Mask 11 1 PAC_ PAC AHB Clock Mask 10 1 APBAMASK APBA Mask 0x14 32 read-write n 0x0 0x0 EIC_ EIC APB Clock Enable 10 1 FREQM_ FREQM APB Clock Enable 11 1 GCLK_ GCLK APB Clock Enable 7 1 MCLK_ MCLK APB Clock Enable 2 1 OSC32KCTRL_ OSC32KCTRL APB Clock Enable 5 1 OSCCTRL_ OSCCTRL APB Clock Enable 4 1 PAC_ PAC APB Clock Enable 0 1 PM_ PM APB Clock Enable 1 1 RSTC_ RSTC APB Clock Enable 3 1 RTC_ RTC APB Clock Enable 9 1 SUPC_ SUPC APB Clock Enable 6 1 TSENS_ TSENS APB Clock Enable 12 1 WDT_ WDT APB Clock Enable 8 1 APBBMASK APBB Mask 0x18 32 read-write n 0x0 0x0 DSU_ DSU APB Clock Enable 1 1 HMATRIXHS_ HMATRIXHS APB Clock Enable 5 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 PORT_ PORT APB Clock Enable 0 1 APBCMASK APBC Mask 0x1C 32 read-write n 0x0 0x0 AC_ AC APB Clock Enable 20 1 ADC0_ ADC0 APB Clock Enable 17 1 ADC1_ ADC1 APB Clock Enable 18 1 CCL_ CCL APB Clock Enable 23 1 DAC_ DAC APB Clock Enable 21 1 EVSYS_ EVSYS APB Clock Enable 0 1 PTC_ PTC APB Clock Enable 22 1 SDADC_ SDADC APB Clock Enable 19 1 SERCOM0_ SERCOM0 APB Clock Enable 1 1 SERCOM1_ SERCOM1 APB Clock Enable 2 1 SERCOM2_ SERCOM2 APB Clock Enable 3 1 SERCOM3_ SERCOM3 APB Clock Enable 4 1 SERCOM4_ SERCOM4 APB Clock Enable 5 1 SERCOM5_ SERCOM5 APB Clock Enable 6 1 TAL_ TAL APB Clock Enable 24 1 TC0_ TC0 APB Clock Enable 12 1 TC1_ TC1 APB Clock Enable 13 1 TC2_ TC2 APB Clock Enable 14 1 TC3_ TC3 APB Clock Enable 15 1 TC4_ TC4 APB Clock Enable 16 1 TCC0_ TCC0 APB Clock Enable 9 1 TCC1_ TCC1 APB Clock Enable 10 1 TCC2_ TCC2 APB Clock Enable 11 1 APBDMASK APBD Mask 0x20 32 read-write n 0x0 0x0 SERCOM6_ SERCOM6 APB Clock Enable 0 1 SERCOM7_ SERCOM7 APB Clock Enable 1 1 TC5_ TC5 APB Clock Enable 2 1 TC6_ TC6 APB Clock Enable 3 1 TC7_ TC7 APB Clock Enable 4 1 CPUDIV CPU Clock Division 0x4 8 read-write n 0x0 0x0 CPUDIV CPU Clock Division Factor 0 8 CPUDIVSelect DIV1 Divide by 1 0x1 DIV16 Divide by 16 0x10 DIV2 Divide by 2 0x2 DIV32 Divide by 32 0x20 DIV4 Divide by 4 0x4 DIV64 Divide by 64 0x40 DIV8 Divide by 8 0x8 DIV128 Divide by 128 0x80 INTENCLR Interrupt Enable Clear 0x1 8 read-write n 0x0 0x0 CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x2 8 read-write n 0x0 0x0 CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x3 8 read-write n 0x0 0x0 CKRDY Clock Ready 0 1 MPU Memory Protection Unit MPU 0x0 0x0 0x14 registers n CTRL MPU Control Register 0x4 32 read-write n 0x0 0x0 ENABLE MPU Enable 0 1 HFNMIENA Enable Hard Fault and NMI handlers 1 1 PRIVDEFENA Enables privileged software access to default memory map 2 1 RASR MPU Region Attribute and Size Register 0x10 32 read-write n 0x0 0x0 AP Access Permission 24 3 B Bufferable bit 16 1 C Cacheable bit 17 1 ENABLE Region Enable 0 1 S Shareable bit 18 1 SIZE Region Size 1 5 SRD Sub-region disable 8 8 TEX TEX bit 19 3 XN Execute Never Attribute 28 1 RBAR MPU Region Base Address Register 0xC 32 read-write n 0x0 0x0 ADDR Region base address 5 27 REGION Region number 0 4 VALID Region number valid 4 1 RNR MPU Region Number Register 0x8 32 read-write n 0x0 0x0 REGION Region referenced by RBAR and RASR 0 8 TYPE MPU Type Register 0x0 32 read-only n 0x0 0x0 DREGION Number of Data Regions 8 8 IREGION Number of Instruction Regions 16 8 SEPARATE Separate instruction and Data Memory MapsRegions 0 1 MTB Cortex-M0+ Micro-Trace Buffer MTB 0x0 0x0 0x1000 registers n AUTHSTATUS MTB Authentication Status 0xFB8 32 read-only n 0x0 0x0 BASE MTB Base 0xC 32 read-only n 0x0 0x0 CID0 Component Identification 0 0xFF0 32 read-only n 0x0 0x0 CID1 Component Identification 1 0xFF4 32 read-only n 0x0 0x0 CID2 Component Identification 2 0xFF8 32 read-only n 0x0 0x0 CID3 Component Identification 3 0xFFC 32 read-only n 0x0 0x0 CLAIMCLR MTB Claim Clear 0xFA4 32 read-write n 0x0 0x0 CLAIMSET MTB Claim Set 0xFA0 32 read-write n 0x0 0x0 DEVARCH MTB Device Architecture 0xFBC 32 read-only n 0x0 0x0 DEVID MTB Device Configuration 0xFC8 32 read-only n 0x0 0x0 DEVTYPE MTB Device Type 0xFCC 32 read-only n 0x0 0x0 FLOW MTB Flow 0x8 32 read-write n 0x0 0x0 AUTOHALT Auto Halt Request 1 1 AUTOSTOP Auto Stop Tracing 0 1 WATERMARK Watermark value 3 29 ITCTRL MTB Integration Mode Control 0xF00 32 read-write n 0x0 0x0 LOCKACCESS MTB Lock Access 0xFB0 32 read-write n 0x0 0x0 LOCKSTATUS MTB Lock Status 0xFB4 32 read-only n 0x0 0x0 MASTER MTB Master 0x4 32 read-write n 0x0 0x0 EN Main Trace Enable 31 1 HALTREQ Halt Request 9 1 MASK Maximum Value of the Trace Buffer in SRAM 0 5 RAMPRIV SRAM Privilege 8 1 SFRWPRIV Special Function Register Write Privilege 7 1 TSTARTEN Trace Start Input Enable 5 1 TSTOPEN Trace Stop Input Enable 6 1 PID0 Peripheral Identification 0 0xFE0 32 read-only n 0x0 0x0 PID1 Peripheral Identification 1 0xFE4 32 read-only n 0x0 0x0 PID2 Peripheral Identification 2 0xFE8 32 read-only n 0x0 0x0 PID3 Peripheral Identification 3 0xFEC 32 read-only n 0x0 0x0 PID4 Peripheral Identification 4 0xFD0 32 read-only n 0x0 0x0 PID5 Peripheral Identification 5 0xFD4 32 read-only n 0x0 0x0 PID6 Peripheral Identification 6 0xFD8 32 read-only n 0x0 0x0 PID7 Peripheral Identification 7 0xFDC 32 read-only n 0x0 0x0 POSITION MTB Position 0x0 32 read-write n 0x0 0x0 POINTER Trace Packet Location Pointer 3 29 WRAP Pointer Value Wraps 2 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0x320 registers n ICER Interrupt Clear Enable Register 0x80 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 31 ICPR Interrupt Clear Pending Register 0x180 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 31 IPR0 Interrupt Priority Register n 0x300 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 IPR1 Interrupt Priority Register n 0x304 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 IPR2 Interrupt Priority Register n 0x308 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 IPR3 Interrupt Priority Register n 0x30C 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 IPR4 Interrupt Priority Register n 0x310 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 IPR5 Interrupt Priority Register n 0x314 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 IPR6 Interrupt Priority Register n 0x318 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 IPR7 Interrupt Priority Register n 0x31C 32 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 ISER Interrupt Set Enable Register 0x0 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 31 ISPR Interrupt Set Pending Register 0x100 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 31 NVMCTRL Non-Volatile Memory Controller NVMCTRL 0x0 0x0 0x2C registers n 0x0 0x30 registers n NVMCTRL_INTREQ 6 NVMCTRL 6 ADDR Address 0x1C 32 read-write n 0x0 0x0 ADDR NVM Address 0 22 CTRLA Control A 0x0 16 read-write n 0x0 0x0 CMD Command 0 7 CMDSelect RWWEEER RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. 0x1a RWWEEWP RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x1c ER Erase Row - Erases the row addressed by the ADDR register. 0x2 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x4 LR Lock Region - Locks the region containing the address location in the ADDR register. 0x40 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x41 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x45 INVALL Invalidate all cache lines. 0x46 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x5 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x6 SF Security Flow Command 0xa WL Write lockbits 0xf CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xa5 CTRLB Control B 0x4 32 read-write n 0x0 0x0 CACHEDIS Cache Disable 18 2 MANW Manual Write 7 1 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 RWS NVM Read Wait States 1 4 RWSSelect SINGLE Single Auto Wait State 0x0 HALF Half Auto Wait State 0x1 DUAL Dual Auto Wait State 0x2 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0x0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 0x1 DISABLED Auto power reduction disabled. 0x3 INTENCLR Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x10 8 read-write n 0x0 0x0 ERROR Error Interrupt Enable 1 1 READY NVM Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 read-write n 0x0 0x0 ERROR Error 1 1 READY NVM Ready 0 1 LOCK Lock Section 0x20 16 read-write n 0x0 0x0 LOCK Region Lock Bits 0 16 read-only PARAM NVM Parameter 0x8 32 read-write n 0x0 0x0 NVMP NVM Pages 0 16 read-only PSZ Page Size 16 3 read-only PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 RWWEEP RWW EEPROM Pages 20 12 read-only PBLDATA0 Page Buffer Load Data 0 0x28 32 read-only n 0x0 0x0 PBLDATA1 Page Buffer Load Data 1 0x2C 32 read-only n 0x0 0x0 STATUS Status 0x18 16 read-write n 0x0 0x0 LOAD NVM Page Buffer Active Loading 1 1 LOCKE Lock Error Status 3 1 NVME NVM Error 4 1 PRM Power Reduction Mode 0 1 read-only PROGE Programming Error Status 2 1 SB Security Bit Status 8 1 read-only OSC32KCTRL 32k Oscillators Control OSC32KCTRL 0x0 0x0 0x2C registers n 0x0 0x20 registers n SYSTEM_INTREQ 0 CFDCTRL Clock Failure Detector Control 0x16 8 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 0 1 CFDPRESC Clock Failure Detector Prescaler 2 1 SWBACK Clock Switch Back 1 1 EVCTRL Event Control 0x17 8 read-write n 0x0 0x0 CFDEO Clock Failure Detector Event Output Enable 0 1 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 CLKFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 CLKFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 CLKFAIL XOSC32K Clock Failure Detector 2 1 OSC32KRDY OSC32K Ready 1 1 XOSC32KRDY XOSC32K Ready 0 1 OSC32K 32kHz Internal Oscillator (OSC32K) Control 0x18 32 read-write n 0x0 0x0 CALIB Oscillator Calibration 16 7 EN1K 1kHz Output Enable 3 1 EN32K 32kHz Output Enable 2 1 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 32 read-write n 0x0 0x0 CALIB Oscillator Calibration 8 5 WRTLOCK Write Lock 15 1 RTCCTRL Clock selection 0x10 32 read-write n 0x0 0x0 RTCSEL RTC Clock Selection 0 3 RTCSELSelect ULP1K 1.024kHz from 32kHz internal ULP oscillator 0x0 ULP32K 32.768kHz from 32kHz internal ULP oscillator 0x1 OSC1K 1.024kHz from 32.768kHz internal oscillator 0x2 OSC32K 32.768kHz from 32.768kHz internal oscillator 0x3 XOSC1K 1.024kHz from 32.768kHz internal oscillator 0x4 XOSC32K 32.768kHz from 32.768kHz external crystal oscillator 0x5 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 CLKFAIL XOSC32K Clock Failure Detector 2 1 read-only CLKSW XOSC32K Clock switch 3 1 read-only OSC32KRDY OSC32K Ready 1 1 read-only XOSC32KRDY XOSC32K Ready 0 1 read-only XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 16 read-write n 0x0 0x0 EN1K 1kHz Output Enable 4 1 EN32K 32kHz Output Enable 3 1 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 XTALEN Crystal Oscillator Enable 2 1 OSCCTRL Oscillators Control OSCCTRL 0x0 0x0 0x2C registers n 0x0 0x3C registers n SYSTEM_INTREQ 0 CAL48M 48MHz Oscillator Calibration 0x38 32 read-write n 0x0 0x0 FCAL Frequency Calibration (48MHz) 0 6 FRANGE Frequency Range (48MHz) 8 2 TCAL Temperature Calibration (48MHz) 16 6 CFDPRESC Cloc Failure Detector Prescaler 0x12 8 read-write n 0x0 0x0 CFDPRESC Clock Failure Detector Prescaler 0 3 DPLLCTRLA DPLL Control 0x1C 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand 7 1 RUNSTDBY Run in Standby 6 1 DPLLCTRLB Digital Core Configuration 0x24 32 read-write n 0x0 0x0 DIV Clock Divider 16 11 FILTER Proportional Integral Filter Selection 0 2 LBYPASS Lock Bypass 12 1 LPEN Low-Power Enable 2 1 LTIME Lock Time 8 3 REFCLK Reference Clock Selection 4 2 WUF Wake Up Fast 3 1 DPLLPRESC DPLL Prescaler 0x28 8 read-write n 0x0 0x0 PRESC Output Clock Prescaler 0 2 PRESCSelect DIV1 DPLL output is divided by 1 0x0 DIV2 DPLL output is divided by 2 0x1 DIV4 DPLL output is divided by 4 0x2 DPLLRATIO DPLL Ratio Control 0x20 32 read-write n 0x0 0x0 LDR Loop Divider Ratio 0 12 LDRFRAC Loop Divider Ratio Fractional Part 16 4 DPLLSTATUS DPLL Status 0x30 8 read-only n 0x0 0x0 CLKRDY DPLL Clock Ready 1 1 read-only LOCK DPLL Lock Status 0 1 read-only DPLLSYNCBUSY DPLL Synchronization Busy 0x2C 8 read-only n 0x0 0x0 DPLLPRESC DPLL Prescaler Synchronization Status 3 1 read-only DPLLRATIO DPLL Ratio Synchronization Status 2 1 read-only ENABLE DPLL Enable Synchronization Status 1 1 read-only EVCTRL Event Control 0x13 8 read-write n 0x0 0x0 CFDEO Clock Failure Detector Event Output Enable 0 1 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 DPLLLCKF DPLL Lock Fall Interrupt Enable 9 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 8 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 11 1 DPLLLTO DPLL Time Out Interrupt Enable 10 1 OSC48MRDY OSC48M Ready Interrupt Enable 4 1 XOSCFAIL XOSC Clock Failure Detector Interrupt Enable 1 1 XOSCRDY XOSC Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 DPLLLCKF DPLL Lock Fall Interrupt Enable 9 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 8 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 11 1 DPLLLTO DPLL Time Out Interrupt Enable 10 1 OSC48MRDY OSC48M Ready Interrupt Enable 4 1 XOSCFAIL XOSC Clock Failure Detector Interrupt Enable 1 1 XOSCRDY XOSC Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 DPLLLCKF DPLL Lock Fall 9 1 DPLLLCKR DPLL Lock Rise 8 1 DPLLLDRTO DPLL Ratio Ready 11 1 DPLLLTO DPLL Timeout 10 1 OSC48MRDY OSC48M Ready 4 1 XOSCFAIL XOSC Clock Failure Detector 1 1 XOSCRDY XOSC Ready 0 1 OSC48MCTRL 48MHz Internal Oscillator (OSC48M) Control 0x14 8 read-write n 0x0 0x0 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 OSC48MDIV OSC48M Divider 0x15 8 read-write n 0x0 0x0 DIV OSC48M Division Factor 0 4 OSC48MSTUP OSC48M Startup Time 0x16 8 read-write n 0x0 0x0 STARTUP Startup Time 0 3 OSC48MSYNCBUSY OSC48M Synchronization Busy 0x18 32 read-only n 0x0 0x0 OSC48MDIV OSC48MDIV Synchronization Status 2 1 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 DPLLLCKF DPLL Lock Fall 9 1 read-only DPLLLCKR DPLL Lock Rise 8 1 read-only DPLLLDRTO DPLL Ratio Ready 11 1 read-only DPLLTO DPLL Timeout 10 1 read-only OSC48MRDY OSC48M Ready 4 1 read-only XOSCCKSW XOSC Clock Switch 2 1 read-only XOSCFAIL XOSC Clock Failure Detector 1 1 read-only XOSCRDY XOSC Ready 0 1 read-only XOSCCTRL External Multipurpose Crystal Oscillator (XOSC) Control 0x10 16 read-write n 0x0 0x0 AMPGC Automatic Amplitude Gain Control 11 1 CFDEN Xosc Clock Failure Detecteor Enable 3 1 ENABLE Oscillator Enable 1 1 GAIN Oscillator Gain 8 3 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Start-Up Time 12 4 SWBEN Xosc Clock Switch Enable 4 1 XTALEN Crystal Oscillator Enable 2 1 PAC Peripheral Access Controller PAC 0x0 0x0 0x2C registers n 0x0 0x44 registers n SYSTEM_INTREQ 0 EVCTRL Event control 0x4 8 read-write n 0x0 0x0 ERREO Peripheral acess error event output 0 1 INTENCLR Interrupt enable clear 0x8 8 read-write n 0x0 0x0 ERR Peripheral access error interrupt disable 0 1 INTENSET Interrupt enable set 0x9 8 read-write n 0x0 0x0 ERR Peripheral access error interrupt enable 0 1 INTFLAGA Peripheral interrupt flag status - Bridge A 0x14 32 read-write n 0x0 0x0 EIC_ EIC 10 1 FREQM_ FREQM 11 1 GCLK_ GCLK 7 1 MCLK_ MCLK 2 1 OSC32KCTRL_ OSC32KCTRL 5 1 OSCCTRL_ OSCCTRL 4 1 PAC_ PAC 0 1 PM_ PM 1 1 RSTC_ RSTC 3 1 RTC_ RTC 9 1 SUPC_ SUPC 6 1 TSENS_ TSENS 12 1 WDT_ WDT 8 1 INTFLAGAHB Bridge interrupt flag status 0x10 32 read-write n 0x0 0x0 DIVAS_ DIVAS 7 1 FLASH_ FLASH 0 1 HPB0_ HPB0 4 1 HPB1_ HPB1 3 1 HPB2_ HPB2 5 1 HPB3_ HPB3 8 1 HSRAMCM0P_ HSRAMCM0P 1 1 HSRAMDSU_ HSRAMDSU 2 1 LPRAMDMAC_ LPRAMDMAC 6 1 INTFLAGB Peripheral interrupt flag status - Bridge B 0x18 32 read-write n 0x0 0x0 DMAC_ DMAC 3 1 DSU_ DSU 1 1 HMATRIXHS_ HMATRIXHS 5 1 MTB_ MTB 4 1 NVMCTRL_ NVMCTRL 2 1 PORT_ PORT 0 1 INTFLAGC Peripheral interrupt flag status - Bridge C 0x1C 32 read-write n 0x0 0x0 AC_ AC 20 1 ADC0_ ADC0 17 1 ADC1_ ADC1 18 1 CAN0_ CAN0 7 1 CAN1_ CAN1 8 1 CCL_ CCL 23 1 DAC_ DAC 21 1 EVSYS_ EVSYS 0 1 PTC_ PTC 22 1 SDADC_ SDADC 19 1 SERCOM0_ SERCOM0 1 1 SERCOM1_ SERCOM1 2 1 SERCOM2_ SERCOM2 3 1 SERCOM3_ SERCOM3 4 1 SERCOM4_ SERCOM4 5 1 SERCOM5_ SERCOM5 6 1 TAL_ TAL 24 1 TC0_ TC0 12 1 TC1_ TC1 13 1 TC2_ TC2 14 1 TC3_ TC3 15 1 TC4_ TC4 16 1 TCC0_ TCC0 9 1 TCC1_ TCC1 10 1 TCC2_ TCC2 11 1 INTFLAGD Peripheral interrupt flag status - Bridge D 0x20 32 read-write n 0x0 0x0 SERCOM6_ SERCOM6 0 1 SERCOM7_ SERCOM7 1 1 TC5_ TC5 2 1 TC6_ TC6 3 1 TC7_ TC7 4 1 STATUSA Peripheral write protection status - Bridge A 0x34 32 read-only n 0x0 0x0 EIC_ EIC APB Protect Enable 10 1 FREQM_ FREQM APB Protect Enable 11 1 GCLK_ GCLK APB Protect Enable 7 1 MCLK_ MCLK APB Protect Enable 2 1 OSC32KCTRL_ OSC32KCTRL APB Protect Enable 5 1 OSCCTRL_ OSCCTRL APB Protect Enable 4 1 PAC_ PAC APB Protect Enable 0 1 PM_ PM APB Protect Enable 1 1 RSTC_ RSTC APB Protect Enable 3 1 RTC_ RTC APB Protect Enable 9 1 SUPC_ SUPC APB Protect Enable 6 1 TSENS_ TSENS APB Protect Enable 12 1 WDT_ WDT APB Protect Enable 8 1 STATUSB Peripheral write protection status - Bridge B 0x38 32 read-only n 0x0 0x0 DMAC_ DMAC APB Protect Enable 3 1 DSU_ DSU APB Protect Enable 1 1 HMATRIXHS_ HMATRIXHS APB Protect Enable 5 1 MTB_ MTB APB Protect Enable 4 1 NVMCTRL_ NVMCTRL APB Protect Enable 2 1 PORT_ PORT APB Protect Enable 0 1 STATUSC Peripheral write protection status - Bridge C 0x3C 32 read-only n 0x0 0x0 AC_ AC APB Protect Enable 20 1 ADC0_ ADC0 APB Protect Enable 17 1 ADC1_ ADC1 APB Protect Enable 18 1 CAN0_ CAN0 APB Protect Enable 7 1 CAN1_ CAN1 APB Protect Enable 8 1 CCL_ CCL APB Protect Enable 23 1 DAC_ DAC APB Protect Enable 21 1 EVSYS_ EVSYS APB Protect Enable 0 1 PTC_ PTC APB Protect Enable 22 1 SDADC_ SDADC APB Protect Enable 19 1 SERCOM0_ SERCOM0 APB Protect Enable 1 1 SERCOM1_ SERCOM1 APB Protect Enable 2 1 SERCOM2_ SERCOM2 APB Protect Enable 3 1 SERCOM3_ SERCOM3 APB Protect Enable 4 1 SERCOM4_ SERCOM4 APB Protect Enable 5 1 SERCOM5_ SERCOM5 APB Protect Enable 6 1 TAL_ TAL APB Protect Enable 24 1 TC0_ TC0 APB Protect Enable 12 1 TC1_ TC1 APB Protect Enable 13 1 TC2_ TC2 APB Protect Enable 14 1 TC3_ TC3 APB Protect Enable 15 1 TC4_ TC4 APB Protect Enable 16 1 TCC0_ TCC0 APB Protect Enable 9 1 TCC1_ TCC1 APB Protect Enable 10 1 TCC2_ TCC2 APB Protect Enable 11 1 STATUSD Peripheral write protection status - Bridge D 0x40 32 read-only n 0x0 0x0 SERCOM6_ SERCOM6 APB Protect Enable 0 1 SERCOM7_ SERCOM7 APB Protect Enable 1 1 TC5_ TC5 APB Protect Enable 2 1 TC6_ TC6 APB Protect Enable 3 1 TC7_ TC7 APB Protect Enable 4 1 WRCTRL Write control 0x0 32 read-write n 0x0 0x0 KEY Peripheral access control key 16 8 KEYSelect OFF No action 0x0 CLR Clear protection 0x1 SET Set protection 0x2 SETLCK Set and lock protection 0x3 PERID Peripheral identifier 0 16 PM Power Manager PM 0x0 0x0 0x2C registers n 0x0 0xA registers n SYSTEM_INTREQ 0 SLEEPCFG Sleep Configuration 0x1 8 read-write n 0x0 0x0 SLEEPMODE Sleep Mode 0 3 SLEEPMODESelect IDLE0 CPU clock is OFF 0x0 IDLE1 AHB clock is OFF 0x1 IDLE2 APB clock are OFF 0x2 STANDBY All Clocks are OFF 0x4 BACKUP Only Backup domain is powered ON 0x5 OFF All power domains are powered OFF 0x6 STDBYCFG Standby Configuration 0x8 16 read-write n 0x0 0x0 BBIASHS Back Bias for HMCRAMCHS 10 2 VREGSMOD Voltage Regulator Standby mode 6 2 VREGSMODSelect AUTO Automatic mode 0x0 PERFORMANCE Performance oriented 0x1 LP Low Power oriented 0x2 PORT Port Module PORT 0x0 0x0 0x200 registers n 0x0 0x180 registers n CTRL Control 0x24 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 CTRL0 Control 0x48 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only CTRL1 Control 0xEC 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only CTRL2 Control 0x210 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only DIR Data Direction 0x0 32 read-write n 0x0 0x0 DIR0 Data Direction 0x0 32 read-write n 0x0 0x0 DIR1 Data Direction 0x80 32 read-write n 0x0 0x0 DIR2 Data Direction 0x180 32 read-write n 0x0 0x0 DIRCLR Data Direction Clear 0x4 32 read-write n 0x0 0x0 DIRCLR0 Data Direction Clear 0x8 32 read-write n 0x0 0x0 DIRCLR1 Data Direction Clear 0x8C 32 read-write n 0x0 0x0 DIRCLR2 Data Direction Clear 0x190 32 read-write n 0x0 0x0 DIRSET Data Direction Set 0x8 32 read-write n 0x0 0x0 DIRSET0 Data Direction Set 0x10 32 read-write n 0x0 0x0 DIRSET1 Data Direction Set 0x98 32 read-write n 0x0 0x0 DIRSET2 Data Direction Set 0x1A0 32 read-write n 0x0 0x0 DIRTGL Data Direction Toggle 0xC 32 read-write n 0x0 0x0 DIRTGL0 Data Direction Toggle 0x18 32 read-write n 0x0 0x0 DIRTGL1 Data Direction Toggle 0xA4 32 read-write n 0x0 0x0 DIRTGL2 Data Direction Toggle 0x1B0 32 read-write n 0x0 0x0 EVCTRL Event Input Control 0x2C 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 EVCTRL0 Event Input Control 0x58 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 EVCTRL1 Event Input Control 0x104 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 EVCTRL2 Event Input Control 0x230 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 IN Data Input Value 0x20 32 read-only n 0x0 0x0 IN0 Data Input Value 0x40 32 read-only n 0x0 0x0 IN1 Data Input Value 0xE0 32 read-only n 0x0 0x0 IN2 Data Input Value 0x200 32 read-only n 0x0 0x0 OUT Data Output Value 0x10 32 read-write n 0x0 0x0 OUT0 Data Output Value 0x20 32 read-write n 0x0 0x0 OUT1 Data Output Value 0xB0 32 read-write n 0x0 0x0 OUT2 Data Output Value 0x1C0 32 read-write n 0x0 0x0 OUTCLR Data Output Value Clear 0x14 32 read-write n 0x0 0x0 OUTCLR0 Data Output Value Clear 0x28 32 read-write n 0x0 0x0 OUTCLR1 Data Output Value Clear 0xBC 32 read-write n 0x0 0x0 OUTCLR2 Data Output Value Clear 0x1D0 32 read-write n 0x0 0x0 OUTSET Data Output Value Set 0x18 32 read-write n 0x0 0x0 OUTSET0 Data Output Value Set 0x30 32 read-write n 0x0 0x0 OUTSET1 Data Output Value Set 0xC8 32 read-write n 0x0 0x0 OUTSET2 Data Output Value Set 0x1E0 32 read-write n 0x0 0x0 OUTTGL Data Output Value Toggle 0x1C 32 read-write n 0x0 0x0 OUTTGL0 Data Output Value Toggle 0x38 32 read-write n 0x0 0x0 OUTTGL1 Data Output Value Toggle 0xD4 32 read-write n 0x0 0x0 OUTTGL2 Data Output Value Toggle 0x1F0 32 read-write n 0x0 0x0 PINCFG0 Pin Configuration n 0x40 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_0 Pin Configuration n - Group 0 0x80 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_1 Pin Configuration n - Group 0 0xC1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_10 Pin Configuration n - Group 0 0x337 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_11 Pin Configuration n - Group 0 0x382 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_12 Pin Configuration n - Group 0 0x3CE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_13 Pin Configuration n - Group 0 0x41B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_14 Pin Configuration n - Group 0 0x469 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_15 Pin Configuration n - Group 0 0x4B8 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_16 Pin Configuration n - Group 0 0x508 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_17 Pin Configuration n - Group 0 0x559 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_18 Pin Configuration n - Group 0 0x5AB 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_19 Pin Configuration n - Group 0 0x5FE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_2 Pin Configuration n - Group 0 0x103 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_20 Pin Configuration n - Group 0 0x652 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_21 Pin Configuration n - Group 0 0x6A7 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_22 Pin Configuration n - Group 0 0x6FD 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_23 Pin Configuration n - Group 0 0x754 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_24 Pin Configuration n - Group 0 0x7AC 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_25 Pin Configuration n - Group 0 0x805 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_26 Pin Configuration n - Group 0 0x85F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_27 Pin Configuration n - Group 0 0x8BA 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_28 Pin Configuration n - Group 0 0x916 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_29 Pin Configuration n - Group 0 0x973 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_3 Pin Configuration n - Group 0 0x146 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_30 Pin Configuration n - Group 0 0x9D1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_31 Pin Configuration n - Group 0 0xA30 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_4 Pin Configuration n - Group 0 0x18A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_5 Pin Configuration n - Group 0 0x1CF 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_6 Pin Configuration n - Group 0 0x215 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_7 Pin Configuration n - Group 0 0x25C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_8 Pin Configuration n - Group 0 0x2A4 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_9 Pin Configuration n - Group 0 0x2ED 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG1 Pin Configuration n 0x41 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG10 Pin Configuration n 0x4A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG11 Pin Configuration n 0x4B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG12 Pin Configuration n 0x4C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG13 Pin Configuration n 0x4D 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG14 Pin Configuration n 0x4E 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG15 Pin Configuration n 0x4F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG16 Pin Configuration n 0x50 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG17 Pin Configuration n 0x51 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG18 Pin Configuration n 0x52 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG19 Pin Configuration n 0x53 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG1_0 Pin Configuration n - Group 1 0x180 read-write n 0x0 0x0 PINCFG1_1 Pin Configuration n - Group 1 0x241 read-write n 0x0 0x0 PINCFG1_10 Pin Configuration n - Group 1 0x937 read-write n 0x0 0x0 PINCFG1_11 Pin Configuration n - Group 1 0xA02 read-write n 0x0 0x0 PINCFG1_12 Pin Configuration n - Group 1 0xACE read-write n 0x0 0x0 PINCFG1_13 Pin Configuration n - Group 1 0xB9B read-write n 0x0 0x0 PINCFG1_14 Pin Configuration n - Group 1 0xC69 read-write n 0x0 0x0 PINCFG1_15 Pin Configuration n - Group 1 0xD38 read-write n 0x0 0x0 PINCFG1_16 Pin Configuration n - Group 1 0xE08 read-write n 0x0 0x0 PINCFG1_17 Pin Configuration n - Group 1 0xED9 read-write n 0x0 0x0 PINCFG1_18 Pin Configuration n - Group 1 0xFAB read-write n 0x0 0x0 PINCFG1_19 Pin Configuration n - Group 1 0x107E read-write n 0x0 0x0 PINCFG1_2 Pin Configuration n - Group 1 0x303 read-write n 0x0 0x0 PINCFG1_20 Pin Configuration n - Group 1 0x1152 read-write n 0x0 0x0 PINCFG1_21 Pin Configuration n - Group 1 0x1227 read-write n 0x0 0x0 PINCFG1_22 Pin Configuration n - Group 1 0x12FD read-write n 0x0 0x0 PINCFG1_23 Pin Configuration n - Group 1 0x13D4 read-write n 0x0 0x0 PINCFG1_24 Pin Configuration n - Group 1 0x14AC read-write n 0x0 0x0 PINCFG1_25 Pin Configuration n - Group 1 0x1585 read-write n 0x0 0x0 PINCFG1_26 Pin Configuration n - Group 1 0x165F read-write n 0x0 0x0 PINCFG1_27 Pin Configuration n - Group 1 0x173A read-write n 0x0 0x0 PINCFG1_28 Pin Configuration n - Group 1 0x1816 read-write n 0x0 0x0 PINCFG1_29 Pin Configuration n - Group 1 0x18F3 read-write n 0x0 0x0 PINCFG1_3 Pin Configuration n - Group 1 0x3C6 read-write n 0x0 0x0 PINCFG1_30 Pin Configuration n - Group 1 0x19D1 read-write n 0x0 0x0 PINCFG1_31 Pin Configuration n - Group 1 0x1AB0 read-write n 0x0 0x0 PINCFG1_4 Pin Configuration n - Group 1 0x48A read-write n 0x0 0x0 PINCFG1_5 Pin Configuration n - Group 1 0x54F read-write n 0x0 0x0 PINCFG1_6 Pin Configuration n - Group 1 0x615 read-write n 0x0 0x0 PINCFG1_7 Pin Configuration n - Group 1 0x6DC read-write n 0x0 0x0 PINCFG1_8 Pin Configuration n - Group 1 0x7A4 read-write n 0x0 0x0 PINCFG1_9 Pin Configuration n - Group 1 0x86D read-write n 0x0 0x0 PINCFG2 Pin Configuration n 0x42 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG20 Pin Configuration n 0x54 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG21 Pin Configuration n 0x55 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG22 Pin Configuration n 0x56 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG23 Pin Configuration n 0x57 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG24 Pin Configuration n 0x58 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG25 Pin Configuration n 0x59 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG26 Pin Configuration n 0x5A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG27 Pin Configuration n 0x5B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG28 Pin Configuration n 0x5C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG29 Pin Configuration n 0x5D 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG2_0 Pin Configuration n - Group 2 0x280 read-write n 0x0 0x0 PINCFG2_1 Pin Configuration n - Group 2 0x3C1 read-write n 0x0 0x0 PINCFG2_10 Pin Configuration n - Group 2 0xF37 read-write n 0x0 0x0 PINCFG2_11 Pin Configuration n - Group 2 0x1082 read-write n 0x0 0x0 PINCFG2_12 Pin Configuration n - Group 2 0x11CE read-write n 0x0 0x0 PINCFG2_13 Pin Configuration n - Group 2 0x131B read-write n 0x0 0x0 PINCFG2_14 Pin Configuration n - Group 2 0x1469 read-write n 0x0 0x0 PINCFG2_15 Pin Configuration n - Group 2 0x15B8 read-write n 0x0 0x0 PINCFG2_16 Pin Configuration n - Group 2 0x1708 read-write n 0x0 0x0 PINCFG2_17 Pin Configuration n - Group 2 0x1859 read-write n 0x0 0x0 PINCFG2_18 Pin Configuration n - Group 2 0x19AB read-write n 0x0 0x0 PINCFG2_19 Pin Configuration n - Group 2 0x1AFE read-write n 0x0 0x0 PINCFG2_2 Pin Configuration n - Group 2 0x503 read-write n 0x0 0x0 PINCFG2_20 Pin Configuration n - Group 2 0x1C52 read-write n 0x0 0x0 PINCFG2_21 Pin Configuration n - Group 2 0x1DA7 read-write n 0x0 0x0 PINCFG2_22 Pin Configuration n - Group 2 0x1EFD read-write n 0x0 0x0 PINCFG2_23 Pin Configuration n - Group 2 0x2054 read-write n 0x0 0x0 PINCFG2_24 Pin Configuration n - Group 2 0x21AC read-write n 0x0 0x0 PINCFG2_25 Pin Configuration n - Group 2 0x2305 read-write n 0x0 0x0 PINCFG2_26 Pin Configuration n - Group 2 0x245F read-write n 0x0 0x0 PINCFG2_27 Pin Configuration n - Group 2 0x25BA read-write n 0x0 0x0 PINCFG2_28 Pin Configuration n - Group 2 0x2716 read-write n 0x0 0x0 PINCFG2_29 Pin Configuration n - Group 2 0x2873 read-write n 0x0 0x0 PINCFG2_3 Pin Configuration n - Group 2 0x646 read-write n 0x0 0x0 PINCFG2_30 Pin Configuration n - Group 2 0x29D1 read-write n 0x0 0x0 PINCFG2_31 Pin Configuration n - Group 2 0x2B30 read-write n 0x0 0x0 PINCFG2_4 Pin Configuration n - Group 2 0x78A read-write n 0x0 0x0 PINCFG2_5 Pin Configuration n - Group 2 0x8CF read-write n 0x0 0x0 PINCFG2_6 Pin Configuration n - Group 2 0xA15 read-write n 0x0 0x0 PINCFG2_7 Pin Configuration n - Group 2 0xB5C read-write n 0x0 0x0 PINCFG2_8 Pin Configuration n - Group 2 0xCA4 read-write n 0x0 0x0 PINCFG2_9 Pin Configuration n - Group 2 0xDED read-write n 0x0 0x0 PINCFG3 Pin Configuration n 0x43 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG30 Pin Configuration n 0x5E 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG31 Pin Configuration n 0x5F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG4 Pin Configuration n 0x44 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG5 Pin Configuration n 0x45 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG6 Pin Configuration n 0x46 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG7 Pin Configuration n 0x47 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG8 Pin Configuration n 0x48 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG9 Pin Configuration n 0x49 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PMUX0 Peripheral Multiplexing n 0x30 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX0_0 Peripheral Multiplexing n - Group 0 0x60 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_1 Peripheral Multiplexing n - Group 0 0x91 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_10 Peripheral Multiplexing n - Group 0 0x277 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_11 Peripheral Multiplexing n - Group 0 0x2B2 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_12 Peripheral Multiplexing n - Group 0 0x2EE 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_13 Peripheral Multiplexing n - Group 0 0x32B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_14 Peripheral Multiplexing n - Group 0 0x369 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_15 Peripheral Multiplexing n - Group 0 0x3A8 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_2 Peripheral Multiplexing n - Group 0 0xC3 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_3 Peripheral Multiplexing n - Group 0 0xF6 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_4 Peripheral Multiplexing n - Group 0 0x12A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_5 Peripheral Multiplexing n - Group 0 0x15F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_6 Peripheral Multiplexing n - Group 0 0x195 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_7 Peripheral Multiplexing n - Group 0 0x1CC 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_8 Peripheral Multiplexing n - Group 0 0x204 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_9 Peripheral Multiplexing n - Group 0 0x23D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX1 Peripheral Multiplexing n 0x31 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX10 Peripheral Multiplexing n 0x3A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX11 Peripheral Multiplexing n 0x3B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX12 Peripheral Multiplexing n 0x3C 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX13 Peripheral Multiplexing n 0x3D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX14 Peripheral Multiplexing n 0x3E 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX15 Peripheral Multiplexing n 0x3F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX1_0 Peripheral Multiplexing n - Group 1 0x160 read-write n 0x0 0x0 PMUX1_1 Peripheral Multiplexing n - Group 1 0x211 read-write n 0x0 0x0 PMUX1_10 Peripheral Multiplexing n - Group 1 0x877 read-write n 0x0 0x0 PMUX1_11 Peripheral Multiplexing n - Group 1 0x932 read-write n 0x0 0x0 PMUX1_12 Peripheral Multiplexing n - Group 1 0x9EE read-write n 0x0 0x0 PMUX1_13 Peripheral Multiplexing n - Group 1 0xAAB read-write n 0x0 0x0 PMUX1_14 Peripheral Multiplexing n - Group 1 0xB69 read-write n 0x0 0x0 PMUX1_15 Peripheral Multiplexing n - Group 1 0xC28 read-write n 0x0 0x0 PMUX1_2 Peripheral Multiplexing n - Group 1 0x2C3 read-write n 0x0 0x0 PMUX1_3 Peripheral Multiplexing n - Group 1 0x376 read-write n 0x0 0x0 PMUX1_4 Peripheral Multiplexing n - Group 1 0x42A read-write n 0x0 0x0 PMUX1_5 Peripheral Multiplexing n - Group 1 0x4DF read-write n 0x0 0x0 PMUX1_6 Peripheral Multiplexing n - Group 1 0x595 read-write n 0x0 0x0 PMUX1_7 Peripheral Multiplexing n - Group 1 0x64C read-write n 0x0 0x0 PMUX1_8 Peripheral Multiplexing n - Group 1 0x704 read-write n 0x0 0x0 PMUX1_9 Peripheral Multiplexing n - Group 1 0x7BD read-write n 0x0 0x0 PMUX2 Peripheral Multiplexing n 0x32 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX2_0 Peripheral Multiplexing n - Group 2 0x260 read-write n 0x0 0x0 PMUX2_1 Peripheral Multiplexing n - Group 2 0x391 read-write n 0x0 0x0 PMUX2_10 Peripheral Multiplexing n - Group 2 0xE77 read-write n 0x0 0x0 PMUX2_11 Peripheral Multiplexing n - Group 2 0xFB2 read-write n 0x0 0x0 PMUX2_12 Peripheral Multiplexing n - Group 2 0x10EE read-write n 0x0 0x0 PMUX2_13 Peripheral Multiplexing n - Group 2 0x122B read-write n 0x0 0x0 PMUX2_14 Peripheral Multiplexing n - Group 2 0x1369 read-write n 0x0 0x0 PMUX2_15 Peripheral Multiplexing n - Group 2 0x14A8 read-write n 0x0 0x0 PMUX2_2 Peripheral Multiplexing n - Group 2 0x4C3 read-write n 0x0 0x0 PMUX2_3 Peripheral Multiplexing n - Group 2 0x5F6 read-write n 0x0 0x0 PMUX2_4 Peripheral Multiplexing n - Group 2 0x72A read-write n 0x0 0x0 PMUX2_5 Peripheral Multiplexing n - Group 2 0x85F read-write n 0x0 0x0 PMUX2_6 Peripheral Multiplexing n - Group 2 0x995 read-write n 0x0 0x0 PMUX2_7 Peripheral Multiplexing n - Group 2 0xACC read-write n 0x0 0x0 PMUX2_8 Peripheral Multiplexing n - Group 2 0xC04 read-write n 0x0 0x0 PMUX2_9 Peripheral Multiplexing n - Group 2 0xD3D read-write n 0x0 0x0 PMUX3 Peripheral Multiplexing n 0x33 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX4 Peripheral Multiplexing n 0x34 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX5 Peripheral Multiplexing n 0x35 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX6 Peripheral Multiplexing n 0x36 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX7 Peripheral Multiplexing n 0x37 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX8 Peripheral Multiplexing n 0x38 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX9 Peripheral Multiplexing n 0x39 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 WRCONFIG Write Configuration 0x28 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 WRCONFIG0 Write Configuration 0x50 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 WRCONFIG1 Write Configuration 0xF8 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 WRCONFIG2 Write Configuration 0x220 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 PORT_IOBUS Port Module PORT 0x0 0x0 0x200 registers n 0x0 0x180 registers n CTRL Control 0x24 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 CTRL0 Control 0x48 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only CTRL1 Control 0xEC 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only CTRL2 Control 0x210 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 write-only DIR Data Direction 0x0 32 read-write n 0x0 0x0 DIR0 Data Direction 0x0 32 read-write n 0x0 0x0 DIR1 Data Direction 0x80 32 read-write n 0x0 0x0 DIR2 Data Direction 0x180 32 read-write n 0x0 0x0 DIRCLR Data Direction Clear 0x4 32 read-write n 0x0 0x0 DIRCLR0 Data Direction Clear 0x8 32 read-write n 0x0 0x0 DIRCLR1 Data Direction Clear 0x8C 32 read-write n 0x0 0x0 DIRCLR2 Data Direction Clear 0x190 32 read-write n 0x0 0x0 DIRSET Data Direction Set 0x8 32 read-write n 0x0 0x0 DIRSET0 Data Direction Set 0x10 32 read-write n 0x0 0x0 DIRSET1 Data Direction Set 0x98 32 read-write n 0x0 0x0 DIRSET2 Data Direction Set 0x1A0 32 read-write n 0x0 0x0 DIRTGL Data Direction Toggle 0xC 32 read-write n 0x0 0x0 DIRTGL0 Data Direction Toggle 0x18 32 read-write n 0x0 0x0 DIRTGL1 Data Direction Toggle 0xA4 32 read-write n 0x0 0x0 DIRTGL2 Data Direction Toggle 0x1B0 32 read-write n 0x0 0x0 EVCTRL Event Input Control 0x2C 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 EVCTRL0 Event Input Control 0x58 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 EVCTRL1 Event Input Control 0x104 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 EVCTRL2 Event Input Control 0x230 32 read-write n 0x0 0x0 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 Port Event Action 1 13 2 EVACT2 Port Event Action 2 21 2 EVACT3 Port Event Action 3 29 2 PID0 Port Event Pin Identifier 0 0 5 PID1 Port Event Pin Identifier 1 8 5 PID2 Port Event Pin Identifier 2 16 5 PID3 Port Event Pin Identifier 3 24 5 PORTEI0 Port Event Enable Input 0 7 1 PORTEI1 Port Event Enable Input 1 15 1 PORTEI2 Port Event Enable Input 2 23 1 PORTEI3 Port Event Enable Input 3 31 1 IN Data Input Value 0x20 32 read-only n 0x0 0x0 IN0 Data Input Value 0x40 32 read-only n 0x0 0x0 IN1 Data Input Value 0xE0 32 read-only n 0x0 0x0 IN2 Data Input Value 0x200 32 read-only n 0x0 0x0 OUT Data Output Value 0x10 32 read-write n 0x0 0x0 OUT0 Data Output Value 0x20 32 read-write n 0x0 0x0 OUT1 Data Output Value 0xB0 32 read-write n 0x0 0x0 OUT2 Data Output Value 0x1C0 32 read-write n 0x0 0x0 OUTCLR Data Output Value Clear 0x14 32 read-write n 0x0 0x0 OUTCLR0 Data Output Value Clear 0x28 32 read-write n 0x0 0x0 OUTCLR1 Data Output Value Clear 0xBC 32 read-write n 0x0 0x0 OUTCLR2 Data Output Value Clear 0x1D0 32 read-write n 0x0 0x0 OUTSET Data Output Value Set 0x18 32 read-write n 0x0 0x0 OUTSET0 Data Output Value Set 0x30 32 read-write n 0x0 0x0 OUTSET1 Data Output Value Set 0xC8 32 read-write n 0x0 0x0 OUTSET2 Data Output Value Set 0x1E0 32 read-write n 0x0 0x0 OUTTGL Data Output Value Toggle 0x1C 32 read-write n 0x0 0x0 OUTTGL0 Data Output Value Toggle 0x38 32 read-write n 0x0 0x0 OUTTGL1 Data Output Value Toggle 0xD4 32 read-write n 0x0 0x0 OUTTGL2 Data Output Value Toggle 0x1F0 32 read-write n 0x0 0x0 PINCFG0 Pin Configuration n 0x40 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_0 Pin Configuration n - Group 0 0x80 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_1 Pin Configuration n - Group 0 0xC1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_10 Pin Configuration n - Group 0 0x337 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_11 Pin Configuration n - Group 0 0x382 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_12 Pin Configuration n - Group 0 0x3CE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_13 Pin Configuration n - Group 0 0x41B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_14 Pin Configuration n - Group 0 0x469 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_15 Pin Configuration n - Group 0 0x4B8 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_16 Pin Configuration n - Group 0 0x508 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_17 Pin Configuration n - Group 0 0x559 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_18 Pin Configuration n - Group 0 0x5AB 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_19 Pin Configuration n - Group 0 0x5FE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_2 Pin Configuration n - Group 0 0x103 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_20 Pin Configuration n - Group 0 0x652 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_21 Pin Configuration n - Group 0 0x6A7 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_22 Pin Configuration n - Group 0 0x6FD 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_23 Pin Configuration n - Group 0 0x754 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_24 Pin Configuration n - Group 0 0x7AC 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_25 Pin Configuration n - Group 0 0x805 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_26 Pin Configuration n - Group 0 0x85F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_27 Pin Configuration n - Group 0 0x8BA 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_28 Pin Configuration n - Group 0 0x916 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_29 Pin Configuration n - Group 0 0x973 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_3 Pin Configuration n - Group 0 0x146 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_30 Pin Configuration n - Group 0 0x9D1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_31 Pin Configuration n - Group 0 0xA30 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_4 Pin Configuration n - Group 0 0x18A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_5 Pin Configuration n - Group 0 0x1CF 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_6 Pin Configuration n - Group 0 0x215 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_7 Pin Configuration n - Group 0 0x25C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_8 Pin Configuration n - Group 0 0x2A4 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG0_9 Pin Configuration n - Group 0 0x2ED 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 write-only INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG1 Pin Configuration n 0x41 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG10 Pin Configuration n 0x4A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG11 Pin Configuration n 0x4B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG12 Pin Configuration n 0x4C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG13 Pin Configuration n 0x4D 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG14 Pin Configuration n 0x4E 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG15 Pin Configuration n 0x4F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG16 Pin Configuration n 0x50 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG17 Pin Configuration n 0x51 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG18 Pin Configuration n 0x52 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG19 Pin Configuration n 0x53 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG1_0 Pin Configuration n - Group 1 0x180 read-write n 0x0 0x0 PINCFG1_1 Pin Configuration n - Group 1 0x241 read-write n 0x0 0x0 PINCFG1_10 Pin Configuration n - Group 1 0x937 read-write n 0x0 0x0 PINCFG1_11 Pin Configuration n - Group 1 0xA02 read-write n 0x0 0x0 PINCFG1_12 Pin Configuration n - Group 1 0xACE read-write n 0x0 0x0 PINCFG1_13 Pin Configuration n - Group 1 0xB9B read-write n 0x0 0x0 PINCFG1_14 Pin Configuration n - Group 1 0xC69 read-write n 0x0 0x0 PINCFG1_15 Pin Configuration n - Group 1 0xD38 read-write n 0x0 0x0 PINCFG1_16 Pin Configuration n - Group 1 0xE08 read-write n 0x0 0x0 PINCFG1_17 Pin Configuration n - Group 1 0xED9 read-write n 0x0 0x0 PINCFG1_18 Pin Configuration n - Group 1 0xFAB read-write n 0x0 0x0 PINCFG1_19 Pin Configuration n - Group 1 0x107E read-write n 0x0 0x0 PINCFG1_2 Pin Configuration n - Group 1 0x303 read-write n 0x0 0x0 PINCFG1_20 Pin Configuration n - Group 1 0x1152 read-write n 0x0 0x0 PINCFG1_21 Pin Configuration n - Group 1 0x1227 read-write n 0x0 0x0 PINCFG1_22 Pin Configuration n - Group 1 0x12FD read-write n 0x0 0x0 PINCFG1_23 Pin Configuration n - Group 1 0x13D4 read-write n 0x0 0x0 PINCFG1_24 Pin Configuration n - Group 1 0x14AC read-write n 0x0 0x0 PINCFG1_25 Pin Configuration n - Group 1 0x1585 read-write n 0x0 0x0 PINCFG1_26 Pin Configuration n - Group 1 0x165F read-write n 0x0 0x0 PINCFG1_27 Pin Configuration n - Group 1 0x173A read-write n 0x0 0x0 PINCFG1_28 Pin Configuration n - Group 1 0x1816 read-write n 0x0 0x0 PINCFG1_29 Pin Configuration n - Group 1 0x18F3 read-write n 0x0 0x0 PINCFG1_3 Pin Configuration n - Group 1 0x3C6 read-write n 0x0 0x0 PINCFG1_30 Pin Configuration n - Group 1 0x19D1 read-write n 0x0 0x0 PINCFG1_31 Pin Configuration n - Group 1 0x1AB0 read-write n 0x0 0x0 PINCFG1_4 Pin Configuration n - Group 1 0x48A read-write n 0x0 0x0 PINCFG1_5 Pin Configuration n - Group 1 0x54F read-write n 0x0 0x0 PINCFG1_6 Pin Configuration n - Group 1 0x615 read-write n 0x0 0x0 PINCFG1_7 Pin Configuration n - Group 1 0x6DC read-write n 0x0 0x0 PINCFG1_8 Pin Configuration n - Group 1 0x7A4 read-write n 0x0 0x0 PINCFG1_9 Pin Configuration n - Group 1 0x86D read-write n 0x0 0x0 PINCFG2 Pin Configuration n 0x42 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG20 Pin Configuration n 0x54 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG21 Pin Configuration n 0x55 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG22 Pin Configuration n 0x56 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG23 Pin Configuration n 0x57 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG24 Pin Configuration n 0x58 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG25 Pin Configuration n 0x59 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG26 Pin Configuration n 0x5A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG27 Pin Configuration n 0x5B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG28 Pin Configuration n 0x5C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG29 Pin Configuration n 0x5D 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG2_0 Pin Configuration n - Group 2 0x280 read-write n 0x0 0x0 PINCFG2_1 Pin Configuration n - Group 2 0x3C1 read-write n 0x0 0x0 PINCFG2_10 Pin Configuration n - Group 2 0xF37 read-write n 0x0 0x0 PINCFG2_11 Pin Configuration n - Group 2 0x1082 read-write n 0x0 0x0 PINCFG2_12 Pin Configuration n - Group 2 0x11CE read-write n 0x0 0x0 PINCFG2_13 Pin Configuration n - Group 2 0x131B read-write n 0x0 0x0 PINCFG2_14 Pin Configuration n - Group 2 0x1469 read-write n 0x0 0x0 PINCFG2_15 Pin Configuration n - Group 2 0x15B8 read-write n 0x0 0x0 PINCFG2_16 Pin Configuration n - Group 2 0x1708 read-write n 0x0 0x0 PINCFG2_17 Pin Configuration n - Group 2 0x1859 read-write n 0x0 0x0 PINCFG2_18 Pin Configuration n - Group 2 0x19AB read-write n 0x0 0x0 PINCFG2_19 Pin Configuration n - Group 2 0x1AFE read-write n 0x0 0x0 PINCFG2_2 Pin Configuration n - Group 2 0x503 read-write n 0x0 0x0 PINCFG2_20 Pin Configuration n - Group 2 0x1C52 read-write n 0x0 0x0 PINCFG2_21 Pin Configuration n - Group 2 0x1DA7 read-write n 0x0 0x0 PINCFG2_22 Pin Configuration n - Group 2 0x1EFD read-write n 0x0 0x0 PINCFG2_23 Pin Configuration n - Group 2 0x2054 read-write n 0x0 0x0 PINCFG2_24 Pin Configuration n - Group 2 0x21AC read-write n 0x0 0x0 PINCFG2_25 Pin Configuration n - Group 2 0x2305 read-write n 0x0 0x0 PINCFG2_26 Pin Configuration n - Group 2 0x245F read-write n 0x0 0x0 PINCFG2_27 Pin Configuration n - Group 2 0x25BA read-write n 0x0 0x0 PINCFG2_28 Pin Configuration n - Group 2 0x2716 read-write n 0x0 0x0 PINCFG2_29 Pin Configuration n - Group 2 0x2873 read-write n 0x0 0x0 PINCFG2_3 Pin Configuration n - Group 2 0x646 read-write n 0x0 0x0 PINCFG2_30 Pin Configuration n - Group 2 0x29D1 read-write n 0x0 0x0 PINCFG2_31 Pin Configuration n - Group 2 0x2B30 read-write n 0x0 0x0 PINCFG2_4 Pin Configuration n - Group 2 0x78A read-write n 0x0 0x0 PINCFG2_5 Pin Configuration n - Group 2 0x8CF read-write n 0x0 0x0 PINCFG2_6 Pin Configuration n - Group 2 0xA15 read-write n 0x0 0x0 PINCFG2_7 Pin Configuration n - Group 2 0xB5C read-write n 0x0 0x0 PINCFG2_8 Pin Configuration n - Group 2 0xCA4 read-write n 0x0 0x0 PINCFG2_9 Pin Configuration n - Group 2 0xDED read-write n 0x0 0x0 PINCFG3 Pin Configuration n 0x43 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG30 Pin Configuration n 0x5E 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG31 Pin Configuration n 0x5F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG4 Pin Configuration n 0x44 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG5 Pin Configuration n 0x45 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG6 Pin Configuration n 0x46 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG7 Pin Configuration n 0x47 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG8 Pin Configuration n 0x48 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PINCFG9 Pin Configuration n 0x49 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Select Peripheral Multiplexer 0 1 PULLEN Pull Enable 2 1 PMUX0 Peripheral Multiplexing n 0x30 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX0_0 Peripheral Multiplexing n - Group 0 0x60 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_1 Peripheral Multiplexing n - Group 0 0x91 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_10 Peripheral Multiplexing n - Group 0 0x277 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_11 Peripheral Multiplexing n - Group 0 0x2B2 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_12 Peripheral Multiplexing n - Group 0 0x2EE 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_13 Peripheral Multiplexing n - Group 0 0x32B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_14 Peripheral Multiplexing n - Group 0 0x369 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_15 Peripheral Multiplexing n - Group 0 0x3A8 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_2 Peripheral Multiplexing n - Group 0 0xC3 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_3 Peripheral Multiplexing n - Group 0 0xF6 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_4 Peripheral Multiplexing n - Group 0 0x12A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_5 Peripheral Multiplexing n - Group 0 0x15F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_6 Peripheral Multiplexing n - Group 0 0x195 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_7 Peripheral Multiplexing n - Group 0 0x1CC 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_8 Peripheral Multiplexing n - Group 0 0x204 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX0_9 Peripheral Multiplexing n - Group 0 0x23D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUX1 Peripheral Multiplexing n 0x31 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX10 Peripheral Multiplexing n 0x3A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX11 Peripheral Multiplexing n 0x3B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX12 Peripheral Multiplexing n 0x3C 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX13 Peripheral Multiplexing n 0x3D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX14 Peripheral Multiplexing n 0x3E 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX15 Peripheral Multiplexing n 0x3F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX1_0 Peripheral Multiplexing n - Group 1 0x160 read-write n 0x0 0x0 PMUX1_1 Peripheral Multiplexing n - Group 1 0x211 read-write n 0x0 0x0 PMUX1_10 Peripheral Multiplexing n - Group 1 0x877 read-write n 0x0 0x0 PMUX1_11 Peripheral Multiplexing n - Group 1 0x932 read-write n 0x0 0x0 PMUX1_12 Peripheral Multiplexing n - Group 1 0x9EE read-write n 0x0 0x0 PMUX1_13 Peripheral Multiplexing n - Group 1 0xAAB read-write n 0x0 0x0 PMUX1_14 Peripheral Multiplexing n - Group 1 0xB69 read-write n 0x0 0x0 PMUX1_15 Peripheral Multiplexing n - Group 1 0xC28 read-write n 0x0 0x0 PMUX1_2 Peripheral Multiplexing n - Group 1 0x2C3 read-write n 0x0 0x0 PMUX1_3 Peripheral Multiplexing n - Group 1 0x376 read-write n 0x0 0x0 PMUX1_4 Peripheral Multiplexing n - Group 1 0x42A read-write n 0x0 0x0 PMUX1_5 Peripheral Multiplexing n - Group 1 0x4DF read-write n 0x0 0x0 PMUX1_6 Peripheral Multiplexing n - Group 1 0x595 read-write n 0x0 0x0 PMUX1_7 Peripheral Multiplexing n - Group 1 0x64C read-write n 0x0 0x0 PMUX1_8 Peripheral Multiplexing n - Group 1 0x704 read-write n 0x0 0x0 PMUX1_9 Peripheral Multiplexing n - Group 1 0x7BD read-write n 0x0 0x0 PMUX2 Peripheral Multiplexing n 0x32 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX2_0 Peripheral Multiplexing n - Group 2 0x260 read-write n 0x0 0x0 PMUX2_1 Peripheral Multiplexing n - Group 2 0x391 read-write n 0x0 0x0 PMUX2_10 Peripheral Multiplexing n - Group 2 0xE77 read-write n 0x0 0x0 PMUX2_11 Peripheral Multiplexing n - Group 2 0xFB2 read-write n 0x0 0x0 PMUX2_12 Peripheral Multiplexing n - Group 2 0x10EE read-write n 0x0 0x0 PMUX2_13 Peripheral Multiplexing n - Group 2 0x122B read-write n 0x0 0x0 PMUX2_14 Peripheral Multiplexing n - Group 2 0x1369 read-write n 0x0 0x0 PMUX2_15 Peripheral Multiplexing n - Group 2 0x14A8 read-write n 0x0 0x0 PMUX2_2 Peripheral Multiplexing n - Group 2 0x4C3 read-write n 0x0 0x0 PMUX2_3 Peripheral Multiplexing n - Group 2 0x5F6 read-write n 0x0 0x0 PMUX2_4 Peripheral Multiplexing n - Group 2 0x72A read-write n 0x0 0x0 PMUX2_5 Peripheral Multiplexing n - Group 2 0x85F read-write n 0x0 0x0 PMUX2_6 Peripheral Multiplexing n - Group 2 0x995 read-write n 0x0 0x0 PMUX2_7 Peripheral Multiplexing n - Group 2 0xACC read-write n 0x0 0x0 PMUX2_8 Peripheral Multiplexing n - Group 2 0xC04 read-write n 0x0 0x0 PMUX2_9 Peripheral Multiplexing n - Group 2 0xD3D read-write n 0x0 0x0 PMUX3 Peripheral Multiplexing n 0x33 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX4 Peripheral Multiplexing n 0x34 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX5 Peripheral Multiplexing n 0x35 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX6 Peripheral Multiplexing n 0x36 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX7 Peripheral Multiplexing n 0x37 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX8 Peripheral Multiplexing n 0x38 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUX9 Peripheral Multiplexing n 0x39 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 WRCONFIG Write Configuration 0x28 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 WRCONFIG0 Write Configuration 0x50 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 WRCONFIG1 Write Configuration 0xF8 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 WRCONFIG2 Write Configuration 0x220 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing Template 24 4 PMUXEN Select Peripheral Multiplexer 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG Registers 30 1 WRPMUX Write PMUX Registers 28 1 PTC Peripheral Touch Controller PTC 0x0 0x0 0x1 reserved n PTC 30 RSTC Reset Controller RSTC 0x0 0x0 0x20 registers n 0x0 0x1 registers n RCAUSE Reset Cause 0x0 8 read-only n 0x0 0x0 BODCORE Brown Out CORE Detector Reset 1 1 BODVDD Brown Out VDD Detector Reset 2 1 EXT External Reset 4 1 POR Power On Reset 0 1 SYST System Reset Request 6 1 WDT Watchdog Reset 5 1 RTC Real-Time Counter RTC 0x0 0x0 0x2C registers n 0x0 0x25 registers n RTC_INTREQ 2 RTC 2 ALARM MODE2_ALARM Alarm n Value 0x20 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x00 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 ALARM1 MODE2 Alarm n Value 0x20 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x0 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 CLOCK MODE2 Clock Value 0x18 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x00 PM PM when CLKREP in 12-hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 COMP MODE0 Compare n Value 0x20 32 read-write n 0x0 0x0 COMP Compare Value 0 32 COMP0 MODE1 Compare n Value 0x20 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COMP1 MODE1 Compare n Value 0x22 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COUNT MODE0 Counter Value 0x18 32 read-write n 0x0 0x0 COUNT Counter Value 0 16 CTRLA MODE1 Control A 0x0 16 read-write n 0x0 0x0 CLKREP Clock Representation 6 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB SWRST Software Reset 0 1 write-only DBGCTRL Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 EVCTRL MODE1 Event Control 0x4 32 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 FREQCORR Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 INTENCLR MODE1 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 write-only PER1 Periodic Interval 1 Interrupt Enable 1 1 write-only PER2 Periodic Interval 2 Interrupt Enable 2 1 write-only PER3 Periodic Interval 3 Interrupt Enable 3 1 write-only PER4 Periodic Interval 4 Interrupt Enable 4 1 write-only PER5 Periodic Interval 5 Interrupt Enable 5 1 write-only PER6 Periodic Interval 6 Interrupt Enable 6 1 write-only PER7 Periodic Interval 7 Interrupt Enable 7 1 write-only INTENSET MODE1 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 INTFLAG MODE1 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 ALARM0 Alarm 0 8 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MASK MODE2_ALARM Alarm n Mask 0x24 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MASK1 MODE2 Alarm n Mask 0x24 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE0 - COMP0 32-bit Counter with Single 32-bit Compare - - MODE0 Compare n Value 0x40 32 read-write n 0x0 0x0 COMP Compare Value 0 32 MODE0 - COUNT 32-bit Counter with Single 32-bit Compare - - MODE0 Counter Value 0x18 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 MODE0 - CTRLA 32-bit Counter with Single 32-bit Compare - - MODE0 Control A 0x0 16 read-write n 0x0 0x0 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb SWRST Software Reset 0 1 write-only MODE0 - DBGCTRL 32-bit Counter with Single 32-bit Compare - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE0 - EVCTRL 32-bit Counter with Single 32-bit Compare - - MODE0 Event Control 0x4 32 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE0 - FREQCORR 32-bit Counter with Single 32-bit Compare - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE0 - INTENCLR 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 write-only PER1 Periodic Interval 1 Interrupt Enable 1 1 write-only PER2 Periodic Interval 2 Interrupt Enable 2 1 write-only PER3 Periodic Interval 3 Interrupt Enable 3 1 write-only PER4 Periodic Interval 4 Interrupt Enable 4 1 write-only PER5 Periodic Interval 5 Interrupt Enable 5 1 write-only PER6 Periodic Interval 6 Interrupt Enable 6 1 write-only PER7 Periodic Interval 7 Interrupt Enable 7 1 write-only MODE0 - INTENSET 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE0 - INTFLAG 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 CMP0 Compare 0 8 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MODE0 - SYNCBUSY 32-bit Counter with Single 32-bit Compare - - MODE0 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 COMP0 COMP 0 Register Busy 5 1 read-only COUNT COUNT Register Busy 3 1 read-only COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only SWRST Software Reset Busy 0 1 read-only MODE1 - COMP0 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x40 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COMP1 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x62 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COUNT 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Value 0x18 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 MODE1 - CTRLA 16-bit Counter with Two 16-bit Compares - - MODE1 Control A 0x0 16 read-write n 0x0 0x0 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb SWRST Software Reset 0 1 write-only MODE1 - DBGCTRL 16-bit Counter with Two 16-bit Compares - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE1 - EVCTRL 16-bit Counter with Two 16-bit Compares - - MODE1 Event Control 0x4 32 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE1 - FREQCORR 16-bit Counter with Two 16-bit Compares - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE1 - INTENCLR 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE1 - INTENSET 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE1 - INTFLAG 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MODE1 - PER 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Period 0x1C 16 read-write n 0x0 0x0 PER Counter Period 0 16 MODE1 - SYNCBUSY 16-bit Counter with Two 16-bit Compares - - MODE1 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 COMP0 COMP 0 Register Busy 5 1 read-only COMP1 COMP 1 Register Busy 6 1 read-only COUNT COUNT Register Busy 3 1 read-only COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only PER PER Register Busy 4 1 read-only SWRST Software Reset Bit Busy 0 1 read-only MODE2 - ALARM0 Clock/Calendar with Alarm - - MODE2 Alarm n Value 0x40 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x0 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CLOCK Clock/Calendar with Alarm - - MODE2 Clock Value 0x18 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x0 PM PM when CLKREP in 12-hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CTRLA Clock/Calendar with Alarm - - MODE2 Control A 0x0 16 read-write n 0x0 0x0 CLKREP Clock Representation 6 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 ENABLE Enable 1 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xa DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xb SWRST Software Reset 0 1 write-only MODE2 - DBGCTRL Clock/Calendar with Alarm - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE2 - EVCTRL Clock/Calendar with Alarm - - MODE2 Event Control 0x4 32 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 MODE2 - FREQCORR Clock/Calendar with Alarm - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE2 - INTENCLR Clock/Calendar with Alarm - - MODE2 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 MODE2 - INTENSET Clock/Calendar with Alarm - - MODE2 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 MODE2 - INTFLAG Clock/Calendar with Alarm - - MODE2 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 ALARM0 Alarm 0 8 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 MODE2 - MASK0 Clock/Calendar with Alarm - - MODE2 Alarm n Mask 0x48 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE2 - SYNCBUSY Clock/Calendar with Alarm - - MODE2 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 ALARM0 ALARM 0 Register Busy 5 1 read-only CLOCK CLOCK Register Busy 3 1 read-only CLOCKSYNC Clock Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only MASK0 MASK 0 Register Busy 11 1 read-only SWRST Software Reset Bit Busy 0 1 read-only PER MODE1 Counter Period 0x1C 16 read-write n 0x0 0x0 PER Counter Period 0 16 SYNCBUSY MODE1 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 ALARM0 ALARM 0 Register Busy 5 1 CLOCK CLOCK Register Busy 3 1 CLOCKSYNC Clock Read Synchronization Enable Bit Busy 15 1 COMP0 COMP 0 Register Busy 5 1 read-only COMP1 COMP 1 Register Busy 6 1 COUNT COUNT Register Busy 3 1 read-only COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 read-only ENABLE Enable Bit Busy 1 1 read-only FREQCORR FREQCORR Register Busy 2 1 read-only MASK0 MASK 0 Register Busy 11 1 PER PER Register Busy 4 1 SWRST Software Reset Bit Busy 0 1 read-only SDADC Sigma-Delta Analog Digital Converter SDADC 0x0 0x0 0x40 registers n 0x0 0x2F registers n SDADC_INTREQ 29 SDADC 29 ANACTRL Analog Control 0x2C 8 read-write n 0x0 0x0 BUFTEST BUFTEST 7 1 CTRSDADC SDADC Control 0 6 ONCHOP Chopper 6 1 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLB Control B 0x2 16 read-write n 0x0 0x0 OSR Over Sampling Ratio 8 3 PRESCALER Prescaler Configuration 0 8 SKPCNT Skip Sample Count 12 4 CTRLC Control C 0xA 8 read-write n 0x0 0x0 FREERUN Free Running Mode 0 1 DBGCTRL Debug Control 0x2E 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x4 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Satrt Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x18 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 14 INPUTCTRL Input Control 0x9 8 read-write n 0x0 0x0 MUXSEL SDADC Input Selection 0 4 MUXSELSelect AIN0 SDADC AIN0 Pin 0x0 AIN1 SDADC AIN1 Pin 0x1 AIN2 SDADC AIN2 Pin 0x2 INTENCLR Interrupt Enable Clear 0x5 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x6 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x7 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 OFFSETCORR Offset Correction 0x14 32 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 24 REFCTRL Reference Control 0x1 8 read-write n 0x0 0x0 ONREFBUF Reference Buffer 7 1 REFRANGE Reference Range 4 2 REFSEL Reference Selection 0 2 REFSELSelect INTREF Internal Bandgap Reference 0x0 AREFB External Reference 0x1 DAC Internal DAC Output 0x2 INTVCC VDDANA 0x3 RESULT Result 0x24 32 read-only n 0x0 0x0 RESERVED Reserved 24 8 read-only RESULT Result Value 0 24 read-only SEQCTRL Sequence Control 0x28 8 read-write n 0x0 0x0 SEQEN Enable Positive Input in the Sequence 0 3 SEQSTATUS Sequence Status 0x8 8 read-only n 0x0 0x0 SEQBUSY Sequence Busy 7 1 read-only SEQSTATE Sequence State 0 4 read-only SHIFTCORR Shift Correction 0x1A 8 read-write n 0x0 0x0 SHIFTCORR Shift Correction Value 0 4 SWTRIG Software Trigger 0x1C 8 read-write n 0x0 0x0 FLUSH SDADC Flush 0 1 START Start SDADC Conversion 1 1 SYNCBUSY Synchronization Busy 0x20 32 read-only n 0x0 0x0 ANACTRL ANACTRL Synchronization Busy 11 1 read-only CTRLC CTRLC Synchronization Busy 2 1 read-only ENABLE ENABLE Synchronization Busy 1 1 read-only GAINCORR GAINCORR Synchronization Busy 8 1 read-only INPUTCTRL INPUTCTRL Synchronization Busy 3 1 read-only OFFSETCORR OFFSETCTRL Synchronization Busy 7 1 read-only SHIFTCORR SHIFTCORR Synchronization Busy 9 1 read-only SWRST SWRST Synchronization Busy 0 1 read-only SWTRIG SWTRG Synchronization Busy 10 1 read-only WINCTRL WINCTRL Synchronization Busy 4 1 read-only WINLT WINLT Synchronization Busy 5 1 read-only WINUT WINUT Synchronization Busy 6 1 read-only WINCTRL Window Monitor Control 0xB 8 read-write n 0x0 0x0 WINMODE Window Monitor Mode 0 3 WINLT Window Monitor Lower Threshold 0xC 32 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 24 WINUT Window Monitor Upper Threshold 0x10 32 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 24 SERCOM0 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM0_6_INTREQ 9 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM1 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM1_7_INTREQ 10 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM2 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM2_INTREQ 11 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM3 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM3_INTREQ 12 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM4 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM4_INTREQ 13 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM5 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM5_INTREQ 14 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM6 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM0_6_INTREQ 9 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM7 Serial Communication Interface SERCOM 0x0 0x0 0x40 registers n 0x0 0x31 registers n SERCOM1_7_INTREQ 10 ADDR SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD1 PAD[2] = TxD PAD[3] = XCK 0x1 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_EXT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 write-only COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 DATA USART_EXT Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 RXPL USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 write-only QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 read-only COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 read-only HS High Speed 10 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 read-only SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_SPI - ADDR SPI Mode - - SPI Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPI - BAUD SPI Mode - - SPI Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPI - CTRLA SPI Mode - - SPI Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DIPO Data In Pinout 20 2 DOPO Data Out Pinout 16 2 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPI - CTRLB SPI Mode - - SPI Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 CHSIZE Character Size 0 3 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPI - DATA SPI Mode - - SPI Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_SPI - DBGCTRL SPI Mode - - SPI Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPI - INTENCLR SPI Mode - - SPI Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPI - INTENSET SPI Mode - - SPI Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPI - INTFLAG SPI Mode - - SPI Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPI - STATUS SPI Mode - - SPI Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 SERCOM_SPI - SYNCBUSY SPI Mode - - SPI Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SERCOM_USART - BAUD USART Mode - - USART Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - BAUD_FRACFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_FRAC_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART - BAUD_USARTFP_MODE USART Mode - - USART Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART - CTRLA USART Mode - - USART Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 ENABLE Enable 1 1 FORM Frame Format 24 4 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 RUNSTDBY Run during Standby 7 1 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SWRST Software Reset 0 1 TXPO Transmit Data Pinout 16 2 SERCOM_USART - CTRLB USART Mode - - USART Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 write-only PMODE Parity Mode 13 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART - CTRLC USART Mode - - USART Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 GTIME RS485 Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 SERCOM_USART - DATA USART Mode - - USART Data 0x28 16 read-write n 0x0 0x0 DATA Data Value 0 9 SERCOM_USART - DBGCTRL USART Mode - - USART Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART - INTENCLR USART Mode - - USART Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART - INTENSET USART Mode - - USART Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART - INTFLAG USART Mode - - USART Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 read-only ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only TXC Transmit Complete Interrupt 1 1 SERCOM_USART - RXPL USART Mode - - USART Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART - STATUS USART Mode - - USART Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 read-only FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 read-only SERCOM_USART - SYNCBUSY USART Mode - - USART Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only STATUS USART_EXT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 read-only COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SWRST Software Reset Synchronization Busy 0 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only SUPC Supply Controller SUPC 0x0 0x0 0x2C registers n 0x0 0x24 registers n SYSTEM_INTREQ 0 BODCORE BODCORE Control 0x14 32 read-write n 0x0 0x0 ACTCFG Configuration in Active mode 8 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD12 generates a reset 0x1 INT The BOD12 generates an interrupt 0x2 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 LEVEL Threshold Level 16 6 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xa DIV4096 Divide clock by 4096 0xb DIV8192 Divide clock by 8192 0xc DIV16384 Divide clock by 16384 0xd DIV32768 Divide clock by 32768 0xe DIV65536 Divide clock by 65536 0xf RUNSTDBY Run during Standby 6 1 STDBYCFG Configuration in Standby mode 5 1 BODVDD BODVDD Control 0x10 32 read-write n 0x0 0x0 ACTCFG Configuration in Active mode 8 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD33 generates a reset 0x1 INT The BOD33 generates an interrupt 0x2 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 LEVEL Threshold Level for VDD 16 6 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xa DIV4096 Divide clock by 4096 0xb DIV8192 Divide clock by 8192 0xc DIV16384 Divide clock by 16384 0xd DIV32768 Divide clock by 32768 0xe DIV65536 Divide clock by 65536 0xf RUNSTDBY Run during Standby 6 1 STDBYCFG Configuration in Standby mode 5 1 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 BCORESRDY BODCORE Synchronization Ready 5 1 BODCOREDET BODCORE Detection 4 1 BODCORERDY BODCORE Ready 3 1 BODVDDDET BODVDD Detection 1 1 BODVDDRDY BODVDD Ready 0 1 BVDDSRDY BODVDD Synchronization Ready 2 1 VREG33RDY VREG33 Ready 6 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 BCORESRDY BODCORE Synchronization Ready 5 1 BODCOREDET BODCORE Detection 4 1 BODCORERDY BODCORE Ready 3 1 BODVDDDET BODVDD Detection 1 1 BODVDDRDY BODVDD Ready 0 1 BVDDSRDY BODVDD Synchronization Ready 2 1 VREG33RDY VREG33 Ready 6 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 BCORESRDY BODCORE Synchronization Ready 5 1 BODCOREDET BODCORE Detection 4 1 BODCORERDY BODCORE Ready 3 1 BODVDDDET BODVDD Detection 1 1 BODVDDRDY BODVDD Ready 0 1 BVDDSRDY BODVDD Synchronization Ready 2 1 VREG33RDY VREG33 Ready 6 1 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 BCORESRDY BODCORE Synchronization Ready 5 1 read-only BODCOREDET BODCORE Detection 4 1 read-only BODCORERDY BODCORE Ready 3 1 read-only BODVDDDET BODVDD Detection 1 1 read-only BODVDDRDY BODVDD Ready 0 1 read-only BVDDSRDY BODVDD Synchronization Ready 2 1 read-only VREG33RDY VREG33 Ready 6 1 read-only VREF VREF Control 0x1C 32 read-write n 0x0 0x0 ONDEMAND On Demand Contrl 7 1 RUNSTDBY Run during Standby 6 1 SEL Voltage Reference Selection 16 4 SELSelect 1V024 1.024V voltage reference typical value 0x0 2V048 2.048V voltage reference typical value 0x2 4V096 4.096V voltage reference typical value 0x3 TSEN Temperature Sensor Output Enable 1 1 VREFOE Voltage Reference Output Enable 2 1 VREG VREG Control 0x18 32 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 VREG33 VREG33 Control 0x20 32 read-write n 0x0 0x0 BYPASS VREG33 Bypass 3 1 ENABLE VREG33 Enable 1 1 ENRDY VREG33 Ready Enable 2 1 ISOEN Isolation Enable 4 1 SystemControl System Control Registers SystemControl 0x0 0x0 0xD34 registers n AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write n 0x0 0x0 ENDIANNESS Data Endianness, 0=little, 1=big 15 1 ENDIANNESSSelect VALUE_0 Little-endian 0 VALUE_1 Big-endian 1 SYSRESETREQ System Reset Request 2 1 SYSRESETREQSelect VALUE_0 No system reset request 0 VALUE_1 Asserts a signal to the outer system that requests a reset 1 VECTCLRACTIVE Debug: Clear state information 1 1 VECTKEY Register key (0x05FA) 16 16 CCR Configuration and Control Register 0xD14 32 read-only n 0x0 0x0 STKALIGN Stack 8-byte aligned on exception entry 9 1 STKALIGNSelect VALUE_0 4-byte aligned 0 VALUE_1 8-byte aligned 1 UNALIGN_TRP Unaligned accesses generates a Hard Fault 3 1 UNALIGN_TRPSelect VALUE_0 Do not trap unaligned halfword and word accesses 0 VALUE_1 Trap unaligned halfword and word accesses 1 CPUID CPUID Base Register 0xD00 32 read-only n 0x0 0x0 ARCHITECTURE Processor Architecture, 0xC=ARMv6-M 16 4 IMPLEMENTER Implementer code, ARM=0x41 24 8 PARTNO Processor Part Number, 0xC60=Cortex-M0+ 4 12 REVISION Minor revision number 0 4 VARIANT Major revision number 20 4 DFSR Debug Fault Status Register 0xD30 32 read-write n 0x0 0x0 BKPT Breakpoint debug event 1 1 DWTTRAP DWT debug event 2 1 EXTERNAL EDBGRQ debug event 4 1 HALTED Halt request debug event active 0 1 VCATCH Vector catch debug event 3 1 ICSR Interrupt Control and State Register 0xD04 32 read-write n 0x0 0x0 ISRPENDING Debug: NVIC interrupt pending 22 1 ISRPREEMPT Debug: Pending exception serviced on exit from debug halt 23 1 NMIPENDSET NMI set-pending bit 31 1 NMIPENDSETSelect VALUE_0 Write: no effect read: NMI exception is not pending 0 VALUE_1 Write: changes NMI exception state to pending read: NMI exception is pending 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the SysTick exception 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSTSETSelect VALUE_0 Write: no effect read: SysTick exception is not pending 0 VALUE_1 Write: changes SysTick exception state to pending read: SysTick exception is pending 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the PendSV exception 1 PENDSVSET PendSV set-pending bit 28 1 PENDSVSETSelect VALUE_0 Write: no effect read: PendSV exception is not pending 0 VALUE_1 Write: changes PendSV exception state to pending read: PendSV exception is pending 1 VECTACTIVE Debug: Exception number of currently executing exception, or 0 if thread mode 0 9 VECTPENDING Exception number of the highest priority pending enabled exception 12 9 SCR System Control Register 0xD10 32 read-write n 0x0 0x0 SEVONPEND Send Event on Pending bit 4 1 SEVONPENDSelect VALUE_0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 VALUE_1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor 1 SLEEPDEEP Uses Deep Sleep as low power mode 2 1 SLEEPDEEPSelect VALUE_0 Sleep 0 VALUE_1 Deep sleep 1 SLEEPONEXIT Sleep-On-Exit when exiting Handler mode 1 1 SLEEPONEXITSelect VALUE_0 O not sleep when returning to Thread mode 0 VALUE_1 Enter sleep, or deep sleep, on return from an ISR 1 SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0x0 SVCALLPENDED 15 1 SHPR2 System Handler Priority Register 2 0xD1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11, SVCall 24 8 SHPR3 System Handler Priority Register 3 0xD20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14, PendSV 16 8 PRI_15 Priority of system handler 15, SysTick exception 24 8 VTOR Vector Table Offset Register 0xD08 32 read-write n 0x0 0x0 TBLOFF Vector table base offset 7 25 SysTick System timer SysTick 0x0 0x0 0x10 registers n CALIB SysTick Calibration Value Register 0xC 32 read-only n 0x0 0x0 NOREF No Separate Reference Clock 31 1 NOREFSelect VALUE_0 The reference clock is provided 0 VALUE_1 The reference clock is not provided 1 SKEW TENMS is rounded from non-integer ratio 30 1 SKEWSelect VALUE_0 10ms calibration value is exact 0 VALUE_1 10ms calibration value is inexact, because of the clock frequency 1 TENMS Reload value to use for 10ms timing 0 24 CSR SysTick Control and Status Register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Clock Source 0=external, 1=processor 2 1 CLKSOURCESelect VALUE_0 External clock 0 VALUE_1 Processor clock 1 COUNTFLAG Timer counted to 0 since last read of register 16 1 ENABLE SysTick Counter Enable 0 1 ENABLESelect VALUE_0 Counter disabled 0 VALUE_1 Counter enabled 1 TICKINT SysTick Exception Request Enable 1 1 TICKINTSelect VALUE_0 Counting down to 0 does not assert the SysTick exception request 0 VALUE_1 Counting down to 0 asserts the SysTick exception request 1 CVR SysTick Current Value Register 0x8 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed 0 24 RVR SysTick Reload Value Register 0x4 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 TAL Trigger Allocator TAL 0x0 0x0 0x2C registers n SYSTEM_INTREQ 0 BRKSTATUS Break Request Status 0xE 16 read-only n 0x0 0x0 CM0P CM0P Break Request 0 2 CM0PSelect INT_RUN CM0P running, by internal request 0x0 INT_HALT CM0P halted, by internal request 0x1 EXT_RUN CM0P running, by external request 0x2 EXT_HALT CM0P halted, by external request 0x3 EVBRK Event Break Request 12 2 EVBRKSelect INT_RUN EVBRK running 0x0 EXTBRK External Break Request 14 2 EXTBRKSelect INT_RUN External CPU running, by internal request 0x0 INT_HALT External CPU halted, by internal request 0x1 EXT_RUN External CPU running, by external request 0x2 EXT_HALT External CPU halted, by external request 0x3 PPP PPP Break Request 2 2 PPPSelect INT_RUN PPP running, by internal request 0x0 INT_HALT PPP halted, by internal request 0x1 EXT_RUN PPP running, by external request 0x2 EXT_HALT PPP halted, by external request 0x3 CTICTRLA0 Cross-Trigger Interface n Control A 0x20 8 read-write n 0x0 0x0 ACTION Action when global break issued 0 2 ACTIONSelect BREAK Break when requested 0x0 INTERRUPT Trigger DBG interrupt instead of break 0x1 IGNORE Ignore break request 0x2 RESTART Action when global restart issued 2 1 CTICTRLA1 Cross-Trigger Interface n Control A 0x32 8 read-write n 0x0 0x0 ACTION Action when global break issued 0 2 ACTIONSelect BREAK Break when requested 0x0 INTERRUPT Trigger DBG interrupt instead of break 0x1 IGNORE Ignore break request 0x2 RESTART Action when global restart issued 2 1 CTICTRLA2 Cross-Trigger Interface n Control A 0x46 8 read-write n 0x0 0x0 ACTION Action when global break issued 0 2 ACTIONSelect BREAK Break when requested 0x0 INTERRUPT Trigger DBG interrupt instead of break 0x1 IGNORE Ignore break request 0x2 RESTART Action when global restart issued 2 1 CTIMASK0 Cross-Trigger Interface n Mask 0x22 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 CTIMASK1 Cross-Trigger Interface n Mask 0x35 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 CTIMASK2 Cross-Trigger Interface n Mask 0x4A 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 DMACPUSEL0 DMA Channel Interrupts CPU Select 0 0x40 32 read-write n 0x0 0x0 CH0 DMA Channel 0 Interrupt CPU Select 0 1 CH1 DMA Channel 1 Interrupt CPU Select 2 1 CH10 DMA Channel 10 Interrupt CPU Select 20 1 CH11 DMA Channel 11 Interrupt CPU Select 22 1 CH2 DMA Channel 2 Interrupt CPU Select 4 1 CH3 DMA Channel 3 Interrupt CPU Select 6 1 CH4 DMA Channel 4 Interrupt CPU Select 8 1 CH5 DMA Channel 5 Interrupt CPU Select 10 1 CH6 DMA Channel 6 Interrupt CPU Select 12 1 CH7 DMA Channel 7 Interrupt CPU Select 14 1 CH8 DMA Channel 8 Interrupt CPU Select 16 1 CH9 DMA Channel 9 Interrupt CPU Select 18 1 EICCPUSEL0 EIC External Interrupts CPU Select 0 0x50 32 read-write n 0x0 0x0 EXTINT0 External Interrupt 0 CPU Select 0 1 EXTINT1 External Interrupt 1 CPU Select 2 1 EXTINT10 External Interrupt 10 CPU Select 20 1 EXTINT11 External Interrupt 11 CPU Select 22 1 EXTINT12 External Interrupt 12 CPU Select 24 1 EXTINT13 External Interrupt 13 CPU Select 26 1 EXTINT14 External Interrupt 14 CPU Select 28 1 EXTINT15 External Interrupt 15 CPU Select 30 1 EXTINT2 External Interrupt 2 CPU Select 4 1 EXTINT3 External Interrupt 3 CPU Select 6 1 EXTINT4 External Interrupt 4 CPU Select 8 1 EXTINT5 External Interrupt 5 CPU Select 10 1 EXTINT6 External Interrupt 6 CPU Select 12 1 EXTINT7 External Interrupt 7 CPU Select 14 1 EXTINT8 External Interrupt 8 CPU Select 16 1 EXTINT9 External Interrupt 9 CPU Select 18 1 EVCPUSEL0 EVSYS Channel Interrupts CPU Select 0 0x48 32 read-write n 0x0 0x0 CH0 Event Channel 0 Interrupt CPU Select 0 1 CH1 Event Channel 1 Interrupt CPU Select 2 1 CH10 Event Channel 10 Interrupt CPU Select 20 1 CH11 Event Channel 11 Interrupt CPU Select 22 1 CH2 Event Channel 2 Interrupt CPU Select 4 1 CH3 Event Channel 3 Interrupt CPU Select 6 1 CH4 Event Channel 4 Interrupt CPU Select 8 1 CH5 Event Channel 5 Interrupt CPU Select 10 1 CH6 Event Channel 6 Interrupt CPU Select 12 1 CH7 Event Channel 7 Interrupt CPU Select 14 1 CH8 Event Channel 8 Interrupt CPU Select 16 1 CH9 Event Channel 9 Interrupt CPU Select 18 1 EVCTRL Event Control 0x6 8 read-write n 0x0 0x0 BRKEI Break Input Event Enable 0 1 BRKEO Break Output Event Enable 1 1 EXTCTRL External Break Control 0x5 8 read-write n 0x0 0x0 ENABLE Enable BRK Pin 0 1 INV Invert BRK Pin 1 1 GLOBMASK Global Break Requests Mask 0xB 8 read-write n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 HALT Debug Halt Request 0xC 8 write-only n 0x0 0x0 CM0P CM0P Break Master 0 1 EVBRK Event Break Master 6 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 INTCPUSEL0 Interrupts CPU Select 0 0x58 32 read-write n 0x0 0x0 INTCPUSEL1 Interrupts CPU Select 1 0x5C 32 read-write n 0x0 0x0 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 BRK Break Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 BRK Break Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 BRK Break 0 1 INTSTATUS0 Interrupt n Status 0x40 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS1 Interrupt n Status 0x61 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS10 Interrupt n Status 0x1B7 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS11 Interrupt n Status 0x1E2 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS12 Interrupt n Status 0x20E 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS13 Interrupt n Status 0x23B 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS14 Interrupt n Status 0x269 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS15 Interrupt n Status 0x298 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS16 Interrupt n Status 0x2C8 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS17 Interrupt n Status 0x2F9 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS18 Interrupt n Status 0x32B 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS19 Interrupt n Status 0x35E 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS2 Interrupt n Status 0x83 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS20 Interrupt n Status 0x392 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS21 Interrupt n Status 0x3C7 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS22 Interrupt n Status 0x3FD 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS23 Interrupt n Status 0x434 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS24 Interrupt n Status 0x46C 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS25 Interrupt n Status 0x4A5 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS26 Interrupt n Status 0x4DF 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS27 Interrupt n Status 0x51A 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS28 Interrupt n Status 0x556 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS29 Interrupt n Status 0x593 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS3 Interrupt n Status 0xA6 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS30 Interrupt n Status 0x5D1 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS4 Interrupt n Status 0xCA 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS5 Interrupt n Status 0xEF 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS6 Interrupt n Status 0x115 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS7 Interrupt n Status 0x13C 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS8 Interrupt n Status 0x164 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 INTSTATUS9 Interrupt n Status 0x18D 8 read-only n 0x0 0x0 IRQ0 Interrupt Status for Interrupt Request 0 within Interrupt n 0 1 IRQ1 Interrupt Status for Interrupt Request 1 within Interrupt n 1 1 IRQ2 Interrupt Status for Interrupt Request 2 within Interrupt n 2 1 IRQ3 Interrupt Status for Interrupt Request 3 within Interrupt n 3 1 IRQ4 Interrupt Status for Interrupt Request 4 within Interrupt n 4 1 IRQ5 Interrupt Status for Interrupt Request 5 within Interrupt n 5 1 IRQ6 Interrupt Status for Interrupt Request 6 within Interrupt n 6 1 IRQ7 Interrupt Status for Interrupt Request 7 within Interrupt n 7 1 IRQTRIG Interrupt Trigger 0x60 16 read-write n 0x0 0x0 ENABLE Trigger Enable 0 1 IRQNUM Interrupt Request Number 1 5 OVERRIDE Interrupt Request Override Value 8 8 RESTART Debug Restart Request 0xD 8 write-only n 0x0 0x0 CM0P CM0P Break Master 0 1 EXTBRK External Break Master 7 1 PPP PPP Break Master 1 1 RSTCTRL Reset Control 0x4 8 read-write n 0x0 0x0 TC0 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC0_5_INTREQ 20 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC1 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC1_6_INTREQ 21 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC2 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC2_7_INTREQ 22 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC3 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC3_INTREQ 23 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC4 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC4_INTREQ 24 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC5 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC0_5_INTREQ 20 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC6 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC1_6_INTREQ 21 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC7 Basic Timer Counter TC 0x0 0x0 0x40 registers n 0x0 0x38 registers n TC2_7_INTREQ 22 CC0 COUNT16 Compare and Capture 0x1C 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT16 Compare and Capture 0x1E 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT16 Compare and Capture Buffer 0x30 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT16 Compare and Capture Buffer 0x32 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CC0 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC1 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CCBUF0 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF1 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT32 - CC0 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC1 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CCBUF0 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF1 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 TC_COUNT8 - CC0 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC1 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CCBUF0 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF1 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0x0 CAPTMIN Minimum capture 0x1 CAPTMAX Maximum capture 0x2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 0x2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 write-only TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 UPDATE Force update of double-buffered register 0x3 READSYNC Force a read synchronization of COUNT 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 STAMP Time stamp capture 0x4 PPW Period catured in CC0, pulse width in CC1 0x5 PWP Period catured in CC1, pulse width in CC0 0x6 PW Pulse width capture 0x7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 read-only STOP Stop Status Flag 0 1 read-only TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 MPWM Match PWM 0x3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TCC0 Timer Counter Control TCC 0x0 0x0 0x80 registers n TCC0_INTREQ 17 TCC0 17 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC0_DITH4 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC0_DITH5 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC0_DITH6 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1_DITH4 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC1_DITH5 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC1_DITH6 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2_DITH4 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC2_DITH5 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC2_DITH6 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3_DITH4 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC3_DITH5 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC3_DITH6 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF0_DITH4 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF0_DITH5 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF0_DITH6 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1_DITH4 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF1_DITH5 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF1_DITH6 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2_DITH4 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF2_DITH5 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF2_DITH6 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3_DITH4 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF3_DITH5 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF3_DITH6 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CC0 Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC0_DITH4 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC0_DITH5 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC0_DITH6 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC1 Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC1_DITH4 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC1_DITH5 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC1_DITH6 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC2 Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC2_DITH4 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC2_DITH5 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC2_DITH6 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC3 Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC3_DITH4 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC3_DITH5 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC3_DITH6 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CCBUF0 Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF0_DITH4 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF0_DITH5 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF0_DITH6 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF1 Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF1_DITH4 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF1_DITH5 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF1_DITH6 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF2 Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF2_DITH4 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF2_DITH5 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF2_DITH6 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF3 Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF3_DITH4 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF3_DITH5 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF3_DITH6 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC1 Timer Counter Control TCC 0x0 0x0 0x80 registers n TCC1_INTREQ 18 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC0_DITH4 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC0_DITH5 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC0_DITH6 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1_DITH4 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC1_DITH5 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC1_DITH6 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2_DITH4 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC2_DITH5 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC2_DITH6 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3_DITH4 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC3_DITH5 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC3_DITH6 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF0_DITH4 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF0_DITH5 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF0_DITH6 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1_DITH4 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF1_DITH5 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF1_DITH6 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2_DITH4 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF2_DITH5 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF2_DITH6 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3_DITH4 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF3_DITH5 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF3_DITH6 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CC0 Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC0_DITH4 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC0_DITH5 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC0_DITH6 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC1 Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC1_DITH4 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC1_DITH5 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC1_DITH6 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC2 Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC2_DITH4 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC2_DITH5 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC2_DITH6 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC3 Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC3_DITH4 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC3_DITH5 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC3_DITH6 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CCBUF0 Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF0_DITH4 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF0_DITH5 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF0_DITH6 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF1 Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF1_DITH4 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF1_DITH5 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF1_DITH6 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF2 Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF2_DITH4 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF2_DITH5 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF2_DITH6 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF3 Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF3_DITH4 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF3_DITH5 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF3_DITH6 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC2 Timer Counter Control TCC 0x0 0x0 0x80 registers n TCC2_INTREQ 19 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC0_DITH4 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC0_DITH5 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC0_DITH6 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1_DITH4 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC1_DITH5 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC1_DITH6 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2_DITH4 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC2_DITH5 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC2_DITH6 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3_DITH4 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC3_DITH5 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC3_DITH6 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF0_DITH4 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF0_DITH5 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF0_DITH6 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1_DITH4 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF1_DITH5 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF1_DITH6 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2_DITH4 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF2_DITH5 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF2_DITH6 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3_DITH4 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF3_DITH5 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF3_DITH6 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6 Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6 Period Buffer 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6 Period 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CC0 Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC0_DITH4 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC0_DITH5 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC0_DITH6 Compare and Capture CC%s 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC1 Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC1_DITH4 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC1_DITH5 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC1_DITH6 Compare and Capture CC%s 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC2 Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC2_DITH4 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC2_DITH5 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC2_DITH6 Compare and Capture CC%s 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC3 Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC3_DITH4 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC3_DITH5 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC3_DITH6 Compare and Capture CC%s 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CCBUF0 Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF0_DITH4 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF0_DITH5 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF0_DITH6 Compare and Capture Buffer CCBUF%s 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF1 Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF1_DITH4 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF1_DITH5 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF1_DITH6 Compare and Capture Buffer CCBUF%s 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF2 Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF2_DITH4 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF2_DITH5 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF2_DITH6 Compare and Capture Buffer CCBUF%s 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF3 Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF3_DITH4 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF3_DITH5 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF3_DITH6 Compare and Capture Buffer CCBUF%s 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6 Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV64 Divide by 64 0x5 DIV256 Divide by 256 0x6 DIV1024 Divide by 1024 0x7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0x0 PRESC Reload or reset counter on next prescaler clock 0x1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 0x2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0x0 DITH4 Dithering is done every 16 PWM frames 0x1 DITH5 Dithering is done every 32 PWM frames 0x2 DITH6 Dithering is done every 64 PWM frames 0x3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0x0 RETRIGGER Clear start, restart or retrigger 0x1 STOP Force stop 0x2 UPDATE Force update or double buffered registers 0x3 READSYNC Force COUNT read synchronization 0x4 DMAOS One-shot DMA trigger 0x5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0x0 SET Set index: cycle B will be forced in the next cycle 0x1 CLEAR Clear index: cycle A will be forced in the next cycle 0x2 HOLD Hold index: the next cycle will be the same as the current cycle 0x3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0x0 END An interrupt/event is generated when a counter cycle ends 0x1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 0x3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0x0 RETRIGGER Start, restart or re-trigger counter on event 0x1 COUNTEV Count on event 0x2 START Start counter on event 0x3 INC Increment counter on event 0x4 COUNT Count on active state of asynchronous event 0x5 STAMP Stamp capture 0x6 FAULT Non-recoverable fault 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0x0 RETRIGGER Re-trigger counter on event 0x1 DIR Direction control 0x2 STOP Stop counter on event 0x3 DEC Decrement counter on event 0x4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x6 FAULT Non-recoverable fault 0x7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0x0 RISE Blanking applied from rising edge of the output waveform 0x1 FALL Blanking applied from falling edge of the output waveform 0x2 BOTH Blanking applied from each toggle of the output waveform 0x3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0x0 CAPT Capture on fault 0x1 CAPTMIN Minimum capture 0x2 CAPTMAX Maximum capture 0x3 LOCMIN Minimum local detection 0x4 LOCMAX Maximum local detection 0x5 DERIV0 Minimum and maximum local detection 0x6 CAPTMARK Capture with ramp index as MSB value 0x7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0x0 CC1 Capture value stored in channel 1 0x1 CC2 Capture value stored in channel 2 0x2 CC3 Capture value stored in channel 3 0x3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0x0 HW Hardware halt action 0x1 SW Software halt action 0x2 NR Non-recoverable fault 0x3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0x0 ENABLE MCEx (x=0,1) event input 0x1 INVERT Inverted MCEx (x=0,1) event input 0x2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 0x3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6 Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6 Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 read-only FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 read-only IDX Ramp 1 1 read-only PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 read-only STOP Stop 0 1 read-only UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0x0 RAMP2A Alternative RAMP2 operation 0x1 RAMP2 RAMP2 operation 0x2 RAMP2C Critical RAMP2 operation 0x3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0x0 MFRQ Match frequency 0x1 NPWM Normal PWM 0x2 DSCRITICAL Dual-slope critical 0x4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 0x7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TSENS Temperature Sensor TSENS 0x0 0x0 0x40 registers n 0x0 0x25 registers n TSENS_INTREQ 5 TSENS 5 CAL Calibration Register 0x20 32 read-write n 0x0 0x0 FCAL Frequency Calibration 0 6 TCAL Temperature Calibration 8 6 CTRLA Control A Register 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 SWRST Software Reset 0 1 CTRLB Control B Register 0x1 8 write-only n 0x0 0x0 START Start Measurement 0 1 write-only CTRLC Control C Register 0x2 8 read-write n 0x0 0x0 FREERUN Free Running Measurement 4 1 WINMODE Window Monitor Mode 0 3 WINMODESelect DISABLE No window mode (default) 0x0 ABOVE VALUE greater than WINLT 0x1 BELOW VALUE less than WINUT 0x2 INSIDE VALUE greater than WINLT and VALUE less than WINUT 0x3 OUTSIDE VALUE less than WINLT or VALUE greater than WINUT 0x4 HYST_ABOVE VALUE greater than WINUT with hysteresis to WINLT 0x5 HYST_BELOW VALUE less than WINLST with hysteresis to WINUT 0x6 DBGCTRL Debug Control Register 0x24 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control Register 0x3 8 read-write n 0x0 0x0 STARTEI Start Conversion Event Input Enable 0 1 STARTINV Start Conversion Event Invert Enable 1 1 WINEO Window Monitor Event Out 2 1 GAIN Gain Register 0x18 32 read-write n 0x0 0x0 GAIN Time Amplifier Gain 0 24 INTENCLR Interrupt Enable Clear Register 0x4 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 OVF Overflow Interrupt Enable 3 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTENSET Interrupt Enable Set Register 0x5 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 OVF Overflow Interrupt Enable 3 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear Register 0x6 8 read-write n 0x0 0x0 OVERRUN Overrun 1 1 OVF Overflow 3 1 RESRDY Result Ready 0 1 WINMON Window Monitor 2 1 OFFSET Offset Register 0x1C 32 read-write n 0x0 0x0 OFFSETC Offset Correction 0 24 STATUS Status Register 0x7 8 read-only n 0x0 0x0 OVF Result Overflow 0 1 read-only SYNCBUSY Synchronization Busy Register 0x8 32 read-only n 0x0 0x0 ENABLE Enable Busy 1 1 read-only SWRST Software Reset Busy 0 1 read-only VALUE Value Register 0xC 32 read-only n 0x0 0x0 VALUE Measurement Value 0 24 read-only WINLT Window Monitor Lower Threshold Register 0x10 32 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 24 WINUT Window Monitor Upper Threshold Register 0x14 32 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 24 WDT Watchdog Timer WDT 0x0 0x0 0x10 registers n WDT_INTREQ 1 WDT 1 CLEAR Clear 0xC 8 write-only n 0x0 0x0 CLEAR Watchdog Clear 0 8 write-only CLEARSelect KEY Clear Key 0xa5 CONFIG Configuration 0x1 8 read-write n 0x0 0x0 PER Time-Out Period 0 4 PERSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb CTRLA Control 0x0 8 read-write n 0x0 0x0 ALWAYSON Always-On 7 1 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 EWCTRL Early Warning Interrupt Control 0x2 8 read-write n 0x0 0x0 EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xa CYC16384 16384 clock cycles 0xb INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EW Early Warning 0 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 ALWAYSON Always-On Busy 3 1 read-only CLEAR Clear Busy 4 1 read-only ENABLE Enable Busy 1 1 read-only WEN Window Enable Busy 2 1 read-only